Explore the PCIe express configuration space, including type zero and type one headers, base address registers, and prefetch memory concepts with root complex, switch, and endpoint examples.

Explore the two PCIe configuration mechanisms—indirect access via cf8/cfc and enhanced indirect access via memory space—covering address/data registers, bus, device, and function addressing, config read/write, and enumeration.

Explore PCIe enumeration, mapping topology from CPU through the root complex to switches and endpoints, via config reads/writes to CF8 and configuration data registers, assigning bus, device, and function numbers.

Learn how PCIe address space is allocated for endpoints and how transactions are routed through root complexes and switches, including base address registers and memory regions.

explains memory request TLP in PCIe Gen 6, detailing three- or four-dw packets, header fields, and payload boundaries. covers first and last byte enables, address translation, and 32-bit addressing.

Explore the completion tlb in PCIe gen 6.0, detailing dw1 fields such as completer id, byte count, byte count modified, and the completion status, including configuration retry and completed abort.

Explore configuration request tlb, detailing the w1–w3 fields, bus/device/function targeting, type zero and type one formats for reads, and a maximum one dw length, followed by io request tlb.

Examine input-output request DLP in the legacy PCA, detailing 3DW components w0, w1, w2 and a 32-bit address space, and introduce message DLP and vendor defined message DLP.

Explore the vendor defined message dlp within pcie gen 6.0, including dw0 to dw3 structure, message code options, and vendor id routing, with type zero and type one tlp handling.

Discover PCIe gen 6.0 transaction ordering, including posted vs non-posted requests and completions, read/write rules, deadlock avoidance, out-of-order completions, and the impact of virtual channels and buffers.

Explore the PCIe Gen 6.0 flit format, packing 236-byte TLPs with 6-byte ECC and 8-byte CRC into a 256-byte flit, using OHC A–E headers.

Compare gen 5.0 and gen 6.0 pci express packet formats, noting tag expansion from 10 to 14 bits and lightweight notification deprecation. Explore updates to memory and i/o requests.

Demonstrates fleet packing and unpacking for PCIe Gen 6.0, detailing TLP segmentation into multiple fleets, DLP, CRC, ECC handling, NOPs, and constraints like eight DLP per half fleet.

Gen 6.0 data link layer operation, including six-byte dlp payloads, fleet types, AC NAC, standard and selective replay, and the replay buffer.

Explore how gen 6.0 standard ack/nak mechanisms manage payload fleets, sequence numbers, and replay using explicit sequence numbers, NOP fleets, and DLP data.

Demonstrates the selective ack/nak mechanism in PCIe gen 6.0, detailing how payload flits are buffered in the RCS replay buffer, acknowledged, replayed, and purged with explicit sequence numbers, nops.

Explore the PCIe Gen6 physical layer, including logical and analog components and link training. Examine ts1/ts2 order sets, crc/ecc, and 1:1 encoding efficiency.

Explore the pipe interface between the MAC and the physical coding sublayer in PCIe, detailing the analog front end, TX/RX signaling, serializers, decoders, and clock data recovery.

Explore non-return-to-zero encoding and eye diagrams, including eye width, eye height, jitter, and leading/trailing edges, to assess signal integrity in NRZ and PAM4 links from transmitter to receiver.

Analyze the analog front end and equalization in PCIe gen 6.0, including cursor coefficients, ctle, dfe, and clock data recovery for minimizing intersymbol interference.

Learn the three clocking architectures for PCIe gen 6.0: shared reference, independent reference, and no reference used, and how clock data recovery and phase locked loops reproduce timing.

Explore the six PCIe Gen 6.0 ordered set types, including training sequences TS1/TS2, skip order sets and electrical idle orders, with 8-to-10 bit encoding, link control fields, and equalization presets.

Explore how the PCIe Gen 6 LTSSM drives link training, from receiver detect to bit and symbol lock, polarity inversion, and lane de-skewing, via TS1/TS2 exchanges.

Learn how PCIe LTSSM handles link initialization and training, including link width and lane negotiation, RTS1/RTS2 exchanges, recovery and speed changes, equalization, and entering the L0 state.

Trace the LTSSM flow from detect to link up, detailing polling, RTS/TS1 exchanges, speed change, and Gen 3 to Gen 5 equalization and link training to L0.

Explore Gen 6 link training in flit mode, including LTSSM state transitions, configuration idle to L0, and the sequence number handshake for starting normal flit exchange.

Explore how LTSSM states are observed and debugged in PCIe Gen 6.0 trackers, including link and lane negotiation, skip orders, and data and transaction layer packets.

Explore Gen 7.0 developments, transitioning from NRC and Pam4 to fiber optics, boosting bandwidth and achieving about twofold speed increases with linear driver optics.