Partial Reconfiguration with FPGA
3.3 (5 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
73 students enrolled

Partial Reconfiguration with FPGA

Learn about the complete Partial Reconfiguration Flow with Xilinx VIVADO and FPGA
3.3 (5 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
73 students enrolled
Created by Digitronix Nepal
Last updated 9/2019
English
English [Auto-generated]
Current price: $104.99 Original price: $149.99 Discount: 30% off
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This course includes
  • 2 hours on-demand video
  • 9 downloadable resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • Partial Reconfiguration Design Flow
  • Xilinx VIVADO tool and FPGA devices for Partial Reconfiguration Flow
  • Debugging the PR Design with ILA and VIO
  • Using PR Controller with VIVADO IP platform and FPGA
  • Using Microblaze and PCIe on PR flow
Requirements
  • Basics of FPGA Design
Description

This course covers the basics of "Partial Reconfiguration (PR)" flow with Xilinx VIVADO tool and FPGA. We have followed the standard syllabus on this training, so the enthusiast who want to learn will get in depth knowledge and skills on the "Partial Reconfiguration". PR flow is necessary when there is larger design and need to fit on the specific series of FPGA. PR flow is followed on the Xilinx as well as Intel-Altera based design tools and FPGA.

This are the major points which covered on this course:

  1. Partial Reconfiguration flow with Xilinx VIVADO and FPGA [7 series, Ultrascale and Ultrascale+ FPGAs]

  2. Using Debugging method [using ILA and VIO] on Partial Reconfiguration flow

  3. Designing PR flow with Partial Reconfigurable Controller

  4. PR flow with MicroBlaze

  5. PCIe based PR flow

  6. BitStream Relocation-overview

Who this course is for:
  • FPGA Design Enthusiast
  • Electrical Engineering and Computer Science Student
Course content
Expand all 12 lectures 02:13:21
+ Introduction
7 lectures 01:17:49
Lab1: Demo on ZedBoard FPGA
02:12
Lab 1 Extra
10:37
Lab 1 Extra: Demo on ZedBoard
02:03
Lab 12: X4R Design and Implementation on ZedBoard with PR Flow
14:26
Lab 12- Demo on ZedBoard FPGA [Implementation of X4r algorithm on ZedBoard]
09:01
+ Debugging with PR Flow
4 lectures 35:35
Debugging PR flow with ILA and VIO in Xilinx VIVADO-Overview
14:01
Debugging PR flow with ILA and VIO in Xilinx VIVADO
11:00
Lab 21: Demo on ZedBoard FPGA
07:49
Lab 21-Extra: Debugging with ILA and VIO
02:45