Partial Reconfiguration with FPGA
What you'll learn
- Partial Reconfiguration Design Flow
- Xilinx VIVADO tool and FPGA devices for Partial Reconfiguration Flow
- Debugging the PR Design with ILA and VIO
- Using PR Controller with VIVADO IP platform and FPGA
Requirements
- Basics of FPGA Design
Description
This course covers the basics of "Partial Reconfiguration (PR)" flow with Xilinx VIVADO tool and FPGA. We have followed the standard syllabus on this training, so the enthusiast who want to learn will get in depth knowledge and skills on the "Partial Reconfiguration". PR flow is necessary when there is larger design and need to fit on the specific series of FPGA. PR flow is followed on the Xilinx as well as Intel-Altera based design tools and FPGA.
This are the major points which covered on this course:
Partial Reconfiguration flow with Xilinx VIVADO and FPGA [7 series, Ultrascale and Ultrascale+ FPGAs]
Using Debugging method [using ILA and VIO] on Partial Reconfiguration flow
Designing PR flow with Partial Reconfigurable Controller
PR flow with MicroBlaze
BitStream Relocation-overview
Who this course is for:
- FPGA Design Enthusiast
- Electrical Engineering and Computer Science Student
Instructor
- 3.6 Instructor Rating
- 1,366 Reviews
- 15,905 Students
- 12 Courses
Digitronix Nepal is an FPGA Design Company serving global customers since 2013. As of the initiative of "Democratizing FPGA Education all over the World", Digitronix Nepal has partnered with LogicTronix [FPGA Design and Machine Learning Company] for creating online learning courses and tutorials on "FPGA, VHDL/Verilog, Computer Vision & Video Processing, High Level Synthesis (HLS), MATLAB/System Generator, Machine Learning Acceleratio, SDAccel, SDSoC, Pynq Development, etc."
Digitronix Nepal believes that with the "Ultra Low Cost and FREE Courses" on FPGA Design, enthusiast from any country can learn and explore on the Field of FPGA Design and grab the global opportunities on FPGA Design, ASIC/VLSI Design and Machine Learning Acceleration.