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Partial Reconfiguration with FPGA
Rating: 3.6 out of 5(21 ratings)
200 students

Partial Reconfiguration with FPGA

Learn about the complete Partial Reconfiguration Flow with Xilinx VIVADO and FPGA
Created byDigitronix Nepal
Last updated 9/2019
English
English [Auto],

What you'll learn

  • Partial Reconfiguration Design Flow
  • Xilinx VIVADO tool and FPGA devices for Partial Reconfiguration Flow
  • Debugging the PR Design with ILA and VIO
  • Using PR Controller with VIVADO IP platform and FPGA

Explore related topics

Course content

3 sections • 12 lectures • 2h 13m total length

  • Partial Reconfiguration Introduction22:52

    Master partial reconfiguration in FPGA design, comparing static and dynamic flows. Learn to partition the fabric into regions and manage reconfigurable modules without downtime.

  • Lab 1: Partial Reconfiguration basic lab16:38

    Learn how to enable partial reconfiguration in a top module, create left and right partitions with a constraints file, and run implementation to generate partial reconfiguration bitstreams.

  • Lab1: Demo on ZedBoard FPGA2:12

    Explore partial reconfiguration on ZedBoard FPGA in a lab demo: learn to select and upload bitstreams, program the device, and compare different implementations and video stream.

  • Lab 1 Extra10:37

    Learn to add extra modules and implement gray box partial configuration in an FPGA project. Explore modular design, tile-based partitions, and configuration processes.

  • Lab 1 Extra: Demo on ZedBoard2:03

    Demonstrate partial reconfiguration on the Zedboard by adding two tiles and comparing tile one and tile two implementations for faster performance and lower latency.

  • Lab 12: X4R Design and Implementation on ZedBoard with PR Flow14:26

    Explore partial reconfiguration flow for on-board X4R design on ZedBoard, partitioning into four algorithm-specific configurations and synthesizing, floor-planning, and implementing a 16-configuration system with timing checks.

  • Lab 12- Demo on ZedBoard FPGA [Implementation of X4r algorithm on ZedBoard]9:01

    Implement the X4r algorithm on the ZedBoard fpga and validate results through simulation and live programming across multiple Blake configurations using a 42 input.

Requirements

  • Basics of FPGA Design

Description

This course covers the basics of "Partial Reconfiguration (PR)" flow with Xilinx VIVADO tool and FPGA. We have followed the standard syllabus on this training, so the enthusiast who want to learn will get in depth knowledge and skills on the "Partial Reconfiguration". PR flow is necessary when there is larger design and need to fit on the specific series of FPGA. PR flow is followed on the Xilinx as well as Intel-Altera based design tools and FPGA.

This are the major points which covered on this course:

  1. Partial Reconfiguration flow with Xilinx VIVADO and FPGA [7 series, Ultrascale and Ultrascale+ FPGAs]

  2. Using Debugging method [using ILA and VIO] on Partial Reconfiguration flow

  3. Designing PR flow with Partial Reconfigurable Controller

  4. PR flow with MicroBlaze

  5. BitStream Relocation-overview

Who this course is for:

  • FPGA Design Enthusiast
  • Electrical Engineering and Computer Science Student

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