Operating system concepts-3

Explore paging, where fixed-size pages and frames move in and out of memory to optimize process execution and reduce fragmentation. Learn how paging tackles fragmentation by selective page allocation.

Paging uses the 90/10 rule to keep only 10 percent of a process in main memory, paging the rest to disk to reduce fragmentation and allow growth.

Learn how paging uses fixed 4 kilobyte pages and frames to eliminate external fragmentation, while internal fragmentation arises from an unused portion of the last page.

Demonstrate how paging maps process pages to noncontinuous main memory frames using a page table and base table to translate virtual addresses into physical addresses.

Describe how paging hardware translates virtual addresses to physical addresses by mapping page numbers and offsets to frames in main memory using a page table.

Learn how paging hardware translates virtual addresses to physical addresses by mapping process pages to memory frames via the page table, preserving offsets.

Explore how paging hardware translates virtual addresses to physical addresses through dynamic relocation. See a simple page-to-frame mapping and how the OS page table directs the transfer.

Derive the page number and offset from a virtual address by dividing by the page size and taking the modulus; with power-of-two sizes, extract directly via bit fields.

Demonstrates address translation from virtual to physical memory using a toy page table, mapping 16-byte pages in a 256-byte memory to frames.

Compute page offset and page number from a virtual address, map virtual page 3 to physical frame 9, and note saving the page table during context switches.

Explore address translation using binary representation instead of division, identifying a six-bit address's page number and page offset, and demonstrate translating virtual to physical and back via the page table.

Compare storing the page table in CPU registers versus main memory to translate virtual addresses to physical addresses, and weigh speed against table size and extra memory accesses.

Explore the translation lookaside buffer, a fully associative page table cache that speeds address translation by caching only needed entries, enabling growth of the page table with the 90/10 rule.

Explore how the translation lookaside buffer (TLB), an associative memory cache, accelerates address translation by caching page-table mappings, handling misses, and applying eviction policies.

Explore how the translation lookaside buffer acts as a fast associative memory that maps page numbers to frame numbers, with valid bits and an optional address space identifier.

Analyze how tlb caches reduce memory access time by comparing hit and miss cases for translating virtual to physical addresses, and present the weighted average of access times.

Allocates k page frames for a process, frees frames if needed, and builds a page table. Flushes the tlb before execution, and loads entries on access using a replacement algorithm.

Analyze context switching with paging by updating the page table base register and process control block, preserving a warm TLB cache, flushing it, and restoring entries for the next process.

Discover how paging enables memory sharing by mapping a single library into multiple processes' virtual memory using shared frames. Learn that reentrant code is read-only and sharing reduces memory usage.

Explore how demand paging uses the hard disk as an extension of main memory, loading only needed pages into RAM via page tables to enable virtual memory and higher multiprogramming.

Explore demand paging in memory, where a page table with a valid bit marks whether a page resides in main memory or on disk, guided by locality and 90/10 rule.

Examine demand paging, where a page table marks pages in memory or on disk, triggering page faults and traps to fetch pages, update the page table, and resume the process.

Compare start-time loading and overlays for page management, highlighting effects on page faults, memory limits, and real-time guarantees in embedded systems.

Explore pure demand paging, where the OS loads pages from disk into RAM only when referenced, triggering page faults and traps, and examine pre paging as a predictor with risks.

Learn demand paging: the page table stores frame numbers and a valid bit for memory residency. On a page fault, the OS loads page from disk and updates its table.

Swap space in virtual memory stores evicted pages on disk to speed future access, using Linux swap partitions or Windows swap files.

Analyze demand paging performance using locality of reference to derive average memory access time and show page faults must be under 1 in a million for acceptable slowdown.

Explain how demand paging uses a TLB and page tables to speed memory access, with hardware or software updates, handling hits and misses and page faults transparently.

Learn how first in, first out page replacement evicts the oldest RAM page to make room for a new page from disk, offering simplicity but risking removal of still-used pages.

Examine the min page replacement algorithm, which evicts the page farthest in the future to minimize page faults, and note its practical limitation: it requires future knowledge or an oracle.

Explore the random page replacement algorithm, which evicts a chosen frame when memory is full. It can perform surprisingly well in large memory systems, but modern systems rarely use it.

Understand how the least recently used eviction policy guides page replacement by evicting the oldest data not accessed for the longest time, and why LRU approximates the min-optimal policy.

Demonstrates fifo page replacement with a three-frame ram, tracing a reference stream of A, B, C, D, and showing seven page faults.

Shows the min page replacement policy with a three-frame ram, evicting the furthest-future page. The example reduces page faults from seven (first-in, first-out) to five in the same reference stream.

Apply the least recently used page eviction policy to a toy memory example, illustrating faults, hits, and frame updates as pages are evicted and loaded.

Show thrashing in the LRU policy when a four-page working set exceeds three frames, causing repeated page faults. Increasing to four frames reduces faults.

Explore how fifo page replacement can increase page faults when a process uses more RAM frames, illustrated by a 3-frame versus 4-frame example with nine faults.

Increasing frames to four demonstrates FIFO faults and evictions with A, B, C, D, E, illustrating Blade's anomaly where more frames raise page faults.

Increase in memory frames reduces page faults under lru page replacement, as the in-memory page set becomes a superset; fifo may not guarantee this, causing anomalies.

Explore thrashing in virtual memory, where caching and page faults force eviction due to a working set that cannot fit in main memory, hurting CPU utilization in multi programming environments.

Limit thrashing in a multi-program environment with a per-process local page replacement algorithm. Evict only a process's own pages when loading a new page.

Explore the working set concept by tracking unique memory pages accessed within a time window delta. Observe how window size p affects accuracy, locality, and RAM frame requirements.

Track page fault frequency per process to prevent thrashing; adjust frames with upper and lower thresholds, and suspend processes when memory is full to balance system-wide page faults.

Demand paging enables virtual memory by letting the address space exceed physical memory and loading only parts the CPU needs, enabling library sharing and reducing page faults and context-switch costs.