Mastering RISC-V in SystemVerilog: From ISA to Working CPU

Explore the RISC-V instruction set architecture, covering r-type, i-type, s-type, b-type, u-type, and j-type, with real examples and 32-bit decoding.

Decode the R-type instruction format in RISC-V, a 32-bit register-to-register operation using fields func7, rs2, rs1, func3, rd, and opcode 0110011.

Explore i-type arithmetic instructions in the RISC-V instruction set, using a single register and a sign-extended 12-bit immediate in a 32-bit format. Explain encoding with rd, rs1, func3, and opcode.

Explore i-type load instructions in risk five instruction set, using base register and 12-bit sign offset to load data and sign-extend to 32 bits, guided by opcode 0000011 and funct3.

JLR executes an indirect jump for function calls by updating the program counter to rs1 plus a signed immediate, saving pc+4, and masking the address to clear bit for alignment.

Identify i-type instructions by their 12-bit immediate, rs1, funct3, and 7-bit opcode. Arithmetic and logic use 0010011, loads use 0000011, and j-type has a unique opcode with funct3=000.

Store data from rs2 into memory using the s-type format. Compute the address as rs1 plus a 12-bit immediate, and encode the operation with opcode 0100011 and a funct3 field.

Learn the B-type in RISC-V: a 32-bit conditional branch using Rs1 and Rs2, with a sign-extended 12-bit immediate shifted left by one and opcode 1100011.

Examine the u-type instruction format and its 20-bit immediate. Shifted left by 12, it becomes upper bits of a 32-bit constant; 0110111 for lui and 0010111 for ipc place it.

Master j-type instructions for unconditional jumps and jump-and-link in RISC-V. Learn saving the return address in Rd and updating PC to PC plus the 20-bit immediate with opcode 1101111.

Explore three processor designs—single cycle, multi-cycle, and pipelined—highlighting how clock cycles, control logic, and datapath affect performance and complexity, with emphasis on hazards and forwarding.

Understand how risk five instructions are structured across type i, s, b, u, and j-type formats, including opcode, funk, and funk seven. The isa defines the software and hardware contract.

Discover how packages centralize constants and types in SystemVerilog, and how structs group signals into a single bundle to keep designs clean, scalable, and easier to debug.

Build an 8-bit ALU that performs not, or, and, xor, plus s.r.l. and mov with a three-bit op selector; demonstrate how a package and struct simplify design.

Learn how SystemVerilog packages centralize shared definitions, moving the ALU op type to a package for reuse, enabling SRL and move operations, easier maintenance, and a clearer RTL design.

Group the ALU inputs a, b, and op into a single alu_t struct, simplifying interfaces and enabling scalable, maintainable systemverilog designs.

Choose packages for shared enums, constants, and type definitions in large multi-module designs like a RISC-V processor, and use structs to group related signals for cleaner, scalable RTL.

Explore how SystemVerilog packages and structs group constants, encodings, and shared control signals to keep the ALU readable and scalable toward a full RISC-V processor.

Design agenda transforms the RISC-V ISA into a working CPU by building hardware blocks: fetch, decode, alu, branches, memory, and registers, wiring them into a modular, pipelining-ready architecture.

Implement a byte-addressable instruction memory as read-only memory that builds 32-bit instructions from four consecutive eight-bit bytes. Configure address width and load contents from a program image file.

Engage with the fetch stage of the risk five processor: the program counter drives memory requests via a request register, delivering 32-bit instructions to the pipeline.

Decode stage builds a shared opcode package, extracts fields and immediate values from 32-bit instructions, and determines instruction type to drive later pipeline stages.

Designs a 32x32 register file for a RISC-V processor with two read addresses ces1 and ces2, one write address rd, and blocks writes to x0; reads are combinational.

Explore building a RISC-V processor ALU in SystemVerilog, defining a shared ALU operation enum, and implementing arithmetic and logic functions, shifts, comparisons, and 32-bit results.

Design a parameterized data memory module for a RISC-V processor, with a memory size enum (byte, halfword, word) and byte-addressable, little-endian load and store supporting sign and zero extension.

Reduce data memory size from 64 kilobytes to 64 bytes for FPGA implementation, enabling lookup table-based distributed memory and preserving single-cycle behavior in this educational RISC-V SystemVerilog project.

Design the risc-v control unit using enums for r-type, i-type, s-type, b-type, u-type, and j-type, plus a writeback source and a control signal struct that maps to the data path.

Integrate all built blocks into a complete single-cycle RISC-V processor inside the top module. Connect memories, program counter, register file, ALU, and control unit to fetch, decode, and execute instructions.

Conclude the design section by implementing the full RISC-V processor in SystemVerilog, building major hardware blocks with clean interfaces for hands-on hardware design and running real programs.

Install Modelsim, learn the full simulation workflow from compiling to loading designs and running a hello world style RISC-V processor with waveform observations.

Install Modelsim by downloading from the official page, selecting the latest release, and completing the Windows installer with default options; launch Modelsim to run your first simulation.

Create a folder with underscores and place the hello world files inside. Open ModelSim, compile all files, run the testbench ending with _tb, and view the hello world transcript.

Run a complete RISC-V program in ModelSim by wiring the RTL modules, testbench, and machine code file, then simulate to observe cycle-by-cycle processor behavior and verify memory updates.

Watch how a RISC-V processor executes software by running a maximum value finder, a Fibonacci generator, and a bubble sort, illustrating software mapping to the RISC-V instruction set.

Learn how to implement a full RISC-V program that finds the maximum value in an array on a custom SystemVerilog core, from algorithm to machine code and simulation.

Demonstrate a full RISC-V fibonacci loop, initializing zero and one, storing results in data memory, and verifying with assembly, machine code encoding, and a simulation.

Demonstrate a full bubble sort on a RISC-V processor, from pseudocode to RISC-V assembly and machine code, sorting a memory array with outer and inner loops.

Ran three real programs on the risc five processor we designed, proving it is fully functional. Extend the instruction set with custom operations to tailor performance for specific workloads.

Run an accelerated grade-scaling program on the RISC-V processor. Identify loops and repeated operations, design a custom instruction to speed them, and compare results to verify performance gains.

Explore a RISC-V grade-scaling program from pseudocode to assembly, machine code, and simulation results, with a baseline 51-clock-cycle run and a path to a custom instruction extension to reduce cycles.

Identify bottlenecks and accelerate by introducing guard, an R-type instruction that uses rs1 to compute pass/fail from a grade, with rd for result, and plan decoder/datapath integration.

Add and implement the custom r-type GRD instruction in the RISC-V processor. Define it as an ALU operation, scale the grade, check pass at 60, and enable writeback to Rd.

Replace the grading loop with a single GRD custom instruction in the RISC-V flow, classifying grades as pass or fail and accelerating execution from 51 to 32 clock cycles.

Analyze a grade scaling program and identify logic. Move logic from software to hardware with a custom instruction set extension on the risk five processor, reducing instructions and boosting performance.

Wrap up the course by showing how RISC-V design in SystemVerilog builds a working CPU through five pipeline stages, instruction types, and key components, enabling program execution and custom extensions.