Mastering Digital VLSI, ASIC and Verilog Interview Questions

Compare asynchronous and synchronous resets, detailing clock independence, edge-triggered reset behavior, internal reset suitability, and the requirement that reset pulses span several clock periods.

Explore why an asynchronous reset can be asserted asynchronously but must be de-asserted synchronously via a two-flip-flop reset synchronization circuit across clock domains.

Compare AHB and AXI: AXI uses separate read and write channels, supports out-of-order transactions and bursts, offering higher bandwidth but higher power; AHB is simpler and lower power.

Blocking assignments in sequential logic update immediately, collapsing a three-flop chain into a single flop and altering data in, data out, and clock behavior compared with non-blocking assignments.

Choose case statements for mutually exclusive conditions controlled by one variable, mapping to FSM state transitions and efficient synthesis with X and Z, versus if-else for non mutually exclusive expressions.

Design an inverter, an and gate, and an or gate using a two-to-one mux by wiring inputs to the select line and grounding inputs, guided by truth tables.

Convert a d flip-flop into a toggle flip-flop by inserting an XOR gate at the input and feeding back the output, enabling toggling on each clock edge.

Design a circuit to delay the falling edge of an input pulse by two clock cycles using registers and flip-flops, producing a stretched output and exploring generic versus fixed solutions.

Model a transitions circuit with a finite state machine to track zero-to-one and one-to-zero transitions in an endless bitstream, and determine which transition type dominates at any point.

Design an eight-bit leading-one detector that outputs the most significant '1' position on the bus. Compare a K-6 statement with a full case implementation, noting code efficiency and synthesizability.

Design a divide-by-three clock from a system clock using a counter and clock enable, covering two versions: duty cycle below 50 percent and a 50 percent duty cycle.

Design a divide-by-three clock with 50 percent duty cycle using a two-bit counter and a negative-edge flip-flop to extend the high period by half a cycle.

Design an eight-bit skip-by-three counter with two counters to alternate increments by one and two, handle reset, and skip multiples of three.

Design a clock divided by two by three using a two-bit counter that cycles 0-1-2, asserting a clock enable to swallow one out of every three source clock cycles.

Duplicate the dense combinational cloud and use a two-to-one mux controlled by the late signal to bypass the delay and resolve the timing violation.

Calculate fifo depth for a bursty bus where the transmitter sends 80 words per 100 cycles and the receiver reads 8 words per 10 cycles, yielding a 32 word depth.

calculate the fifo depth by comparing transmitter write rate at 100 mhz with receiver read rate at 80 mhz; divide time difference by the higher period to get 20 words.

Design a minmax four circuit by wiring two minmax two components for four inputs (x0–x3) and a final stage to determine the ascending min and max outputs.

Design a minmax six circuit by combining minmax two and minmax four components; in second stage wire max outputs to a minmax two and min outputs to another.

Design a circuit with minimum logic that converts a single digit BCD input to the BCD for input times five. Use four-bit BCD digits and direct wiring.

Swap the contents of registers x and y with an xor swap: x <- x xor y, y <- x xor y, then x <- x xor y.

Compare the inbuilt binary counter and the gray counter by counting toggles and per-cell dissipation, concluding the gray counter consumes more power.

Count the number of ones in a seven-bit vector using cascaded full adders to produce a 3-bit count, where sum gives the lower bits and carry the upper bit.

Design a generic combinational circuit to count ones in a bus of any width, using a for loop and a width-determined output via ceiling log2, in Verilog.

Design a random delay circuit detector using cross-correlation to compare two input streams, with a one-to-ten clock cycle delay; implement a parameterized code solution and accompanying article.

Downsize to ten wires and use alternating patterns to detect wiring mismatches between block a and block b; four patterns suffice for ten wires, generalizing to the ceiling of log2(n).

Implement a fibonacci sequence in SystemVerilog using two registers for the preceding values, a counter, and a parameterized end length with a 32-bit output.

Design a circuit to count the rising edges up to seven of an input signal using a ripple counter, and discuss asynchronous clocking and timing implications.

Modify a ripple counter to count both rising and falling edges by using the input signal as the least significant bit, creating a four-bit counter that counts all 16 edges.

Design a circuit to detect the five bit pattern 10110 using the sliding window LFA method. Compare FSM and LFA approaches, noting fixed versus generic patterns and simple verification.

Examine a common clock domain crossing problem where a one-bit control signal may glitch and be mis-sampled despite double-flop synchronization. Register the signal before crossing to ensure reliable transmission.

Learn how to convert a standard d flip-flop into a version with an active low soft reset by adding external gates to the enable and data inputs, preserving modularity.