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Machine Learning for Embedded Systems with ARM Ethos-U NPU

Name: Machine Learning for Embedded Systems with ARM Ethos-U NPU
Rating: 4.6 (86 reviews)

Learn AI, ML, and TensorFlow Lite for microcontrollers with ARM NPU

Created byWadix Technologies

Last updated 11/2025

English

What you'll learn

Learn the Full Workflow of Tiny Machine Learning Model on Embedded Devices
Understand How Testor Flow Lite for Microcontroller (TFLM) Library will be parse and run the Machine Learning Model underence on your embedded device
Understand the Standard Machine Learning Models Limitations on Embedded Systems and the needs to have different and optimized flow for Limited Resources Devices
Learn How ARM had helped to create and define dedicated hardware , architectures and compiler to allow Machine Larning Model Inference on embedded devices
You will get to lear ARM based Machine Learning Hardware Accelerators families (Ethos-U) and associated System On Chip Design Integration of those Accelerators

Course content

12 sections • 109 lectures • 6h 0m total length

Understanding the difference between Model Training and Model Inference5:20
Machine Learning Model Inference2:24
Embedded Devices as End Product for Model Inference2:01
Setup Guide Slide and Repository Links0:12

Tiny Machine Learning Model Developement Flow4:50
Different Machine Learning Models Overview3:15
Standard Trained ML Models Challenge on Embedded Devices3:27
CNN Model As Use Case for Embedded Devices9:27
Convolution Stage5:57
Activation (RELU) Satge1:33
Pooling (Optional) Stage1:57
Stacking Multiple Layers1:38
Flatten1:31
Dense/Connected Layer3:27
Explore how a dense (connected) layer compares a flattened cnn output against reference images using 1d filters and biases to produce neuron outputs that form a probability distribution for recognition.
SoftMax and Final Decision3:16
ML Model Stages & Model Selection for Embedded Devices

Vela Compiler Use Case2:21
Vela Compiler Work Flow Overview3:57
Explore how TensorFlow Lite models are optimized for embedded devices through pruning, clustering, and quantization, then compiled by Vela to generate hardware-specific commands and a ready-to-integrate TensorFlow Lite file.
Vela Compiler Installation Pre-requisites0:39
Vela Compiler Installation1:27
Install the Arm Ethos-U Vela compiler by meeting prerequisites like Python 3.10 and Visual C++ tools, then install via pip3 or source method and verify with Vela version.
Vela Compiler Supported Commands Line Summary3:47
The Vela compiler exposes command line options to view version, generate micro operation reports, and configure ETHOS-U NPU or CPU via tuning and configuration files, with MACs up to 2048.
Vela Compiler System Configuration File Overview0:44
System Configuration File: Memory Configurations Modes4:25
Understand how the NPU uses four memory types—const, arena, cache, and arena cache size—to store weights, bias, and feature maps, and how the three SRAM modes govern data placement.
Vela Compiler Tuning Configuration File1:43
ML Model Compilation Stage

.TFLite Vela Compiled Output File Generation Summary3:50
Flat Buffer File Format1:17
Dump the Vela Output .TFLite Flat Buffer to JSON File Format Representation1:24
Dump and convert a TensorFlow Lite model to JSON using the flatc tool from Google, then explore the model structure with the resulting JSON files.
Flat Buffer File JSON presentation Example3:44
Explore the flat buffer file json presentation of a TensorFlow Lite model, detailing version, opcodes, buffers, and the subgraph with inputs, outputs, tensors, and operators.
Flat Buffer Elements: Opcode Table Section1:18
Flat Buffer Elements: Buffers Section2:03
Flat Buffer Elements: SubGraph Section10:25
Flat Buffer Elements: Machine Learning Operators Opcodes Indexing1:35
Flat Buffer Elements: Tensors Indexing3:45
Describe how flat buffer tensors indexing uses an indexing topology to map inputs, weights, and bias to tensor entries and a temporary output for convolution, improving readability of buffers.
Flat Buffer Elements: Buffers Indexing1:52
NPU CUstom Operation ETHOSU_CONV_2D4:20
ETHOSU_CONV_2D NPU Operation Data Stream2:27
ETHOSU_CONV_2D NPU Operation Embedded Memory Informations1:20
.TFLite Flat Buffer File Metadata Informations Part12:09
.TFLite Flat Buffer File Metadata Informations Part2 (Memory Usage)1:01
.TFLite Flat Buffer File Metadata Informations Part3 (Architecture Config)0:57
.TFLite Flat Buffer File Metadata Example Summary0:31
Inspect metadata appended to the flat buffer from the Vela compilation stage to reveal memory usage, memory types for low-level machine learning, low-level operations, tensor allocations, and related information.

ETHOSU_CONV_2D Operator Input Data Stream Overview4:31
Explore the ETHOS-U NPU input data stream, detailing low-level opcodes for convolutions and activations, DMA transfer commands, memory region addressing, and looping and tiling of tensors to fit microcontroller SRAM.
DMA Transfer Commands3:22
DMA Transfer Commands Summary3:16
Memory Regions Informations2:09
Explain memory regions information for the NPU, including tensor buffers: inputs, outputs, weights, scratches; read-write compatibility, and coordination of CPU and NPU memory layouts to avoid race conditions.
Looping and Tiling Logic Overview2:03
Explore how looping and tiling logic breaks tensors into tiles to fit limited memory, with the Vela compiler generating DMA commands, loop control, and micro-operations for NPU convolution.
Tiling Logic4:45
NPU Micro-Operations2:19

High Performance Vs Low Power ARM ETHOS NPUs (ETHOS-U Vs ETHOS-N)1:52
ARM ETHOS-U Low Power NPUs Usage7:09
ARM Cortex-M55 + Ethos-U Hardware System Integration Overview3:58
ARM Cortex-M55 + Ethos-U Hardware System Integration Example4:07
ARM Ethos-U & Cortex-M/A System Inegration Topologies7:39
ARM NPU Hardware Block Diagram Overview4:10
NPU Functional Block Diagram3:07
NPU System Integration Design Decision

TFLM Top Level Flow2:48
TFLM Interpreter Initialization Stage3:44
TFLM Initialization: Arena Memory Allocation2:30
TFLM Initialization: Interpreter Instantiation Part12:15
TFLM Initialization: Interpreter Instantiation Part21:11
TFLM Nodes Allocation: Tensors Allocation Part13:24
TFLM Nodes Allocation: Tensors Allocation Part24:13
TFLM Nodes Allocation: Tensors Allocation Part31:41
TFLM Nodes Allocation: Tensors Allocation Part40:49
Use the local allocator to create a TensorFlow Lite tensors list for all model tensors, embedding type, buffer pointers, quantization, shape, and constant versus dynamic memory to drive operation execution.
TFLM Operators Invokation Overview1:10
TFLM Operators Invokation: Kernel & DSP Based Operators2:07
TFLM Operators Invokation: Custom NPU Ethos-U Based Operator4:25
TensorFlow Lite Micro Mastery: Interpreter Setup, Memory Arena & Accelerator Dis

ARM CMSIS-NN Role in Machine Learning Execution Flow2:55
CMSIS-NN As Neural Library for Cortex-M Micro-Processors2:10
CMSIS-NN Software Architecture Design4:04
CMSIS-NN Compile Time Feature Flags Selection3:15
CMSIS-NN APIs Summary1:44
Explore how CMSIS-NN APIs map to neural network layers, showing multiple low-level functions per operation, data-type and pooling scheme variations, and CPU feature considerations.
CMSIS-NN Processors Targets Specific Implementation4:47

Alif E7 System on Chip Hardware Block Diagram3:49
Alif E7: High Performance (HP) vs High Efficiency (HE) ETHOS-U55 ARM NPUs1:18
Compare ETHOS-U55 128 and 256 models, noting 128 vs 256 MAC units for low power and high performance machine learning; 128 suits keyword spotting, 256 suits vision workloads.
Alif E7 Development Kit1:24
Select the Alif E7 development kit with Ethos-U55 NPU for embedded machine learning, featuring a dedicated subsystem, lcd-tft display, and a dedicated camera interface for vision-based, low-power tasks.
Alif E7 Development Kit Schematic Overview2:26
Alif E7 Development Kit Jumpers Configuration2:40
Alif E7 Development Kit Presentation2:14
Booting Alif E7 Development Kit2:15
Live Booting of Alif E7 ML Development Kit1:45
Alif E7 Development Kit Builtin Example0:55

Requirements

You should have some understanding of embedded systems based devices and their limitations
Some basic understanding of ARM based architectures and System integration

Description

Machine Learning for Embedded Systems with ARM Ethos-U

Are you ready to bring the power of machine learning into the world of embedded systems?
This course takes you on a complete, hands-on journey from building and training models to running them on real ARM-based hardware with dedicated NPUs.

Most ML courses stop at theory or training. This one goes further: you’ll actually deploy and run models on embedded devices, bridging the gap between machine learning and practical engineering.

What you’ll learn

The core ML theory behind embedded AI

Understand the stages of a neural network execution pipeline
Explore convolution, flattening, activation functions, and softmax in CNNs
Learn how ML operations are optimized for resource-constrained devices

Model preparation workflow

Train models in TensorFlow
Convert them into lightweight .tflite models
Optimize and compile with the ARM Vela compiler for the Ethos-U NPU

Running inference on embedded devices

Execute models with TensorFlow Lite Micro (TFLM) in C++
See how ML operations map to CMSIS-NN kernels and the Ethos-U hardware accelerator
Understand the complete inference path — from model to silicon

Hands-on with real hardware

Set up and run the Alif E7 ML Development Kit
Build and deploy Keyword Spotting and Image Classification demos
Observe real-time outputs directly on the device

Why this course is unique

Bridges the gap between ML theory and real embedded deployment
Covers the entire workflow — from training to NPU execution
Practical, hardware-driven approach using the Alif E7 ML dev kit
Projects designed for easy reproduction on a Windows machine

By the end of this course, you’ll have the confidence and skills to run ML models efficiently on modern embedded systems, skills that are in high demand across IoT, robotics, and edge AI applications.

Whether you’re an embedded engineer ready to add AI to your skill set, or a machine learning practitioner eager to deploy models on hardware accelerators, this course will give you a competitive edge in the future of AI and embedded systems.

Enroll now and start building the next generation of embedded AI applications!

Who this course is for:

Embedded Systems developers who wants to start learning Machine Learning for embedded devices

Machine Learning for Embedded Systems with ARM Ethos-U NPU

What you'll learn

Explore related topics

Course content

Getting Started with the Course4 lectures • 10min

Machine Learning For Embedded Devices Architecture Overview11 lectures • 40min

Tensor Flow Lite For Microcontroller Based Model5 lectures • 14min

ARM NPU Vela Compiler8 lectures • 19min

TFLM Based Machine Learning FlatBuffer for ARM NPU Based Hardware17 lectures • 44min

ARM Ethos-U NPU Input Data Stream7 lectures • 22min

ARM ETHOS-U/N NPU (Embedded AI Hardware Accelerators) Families7 lectures • 32min

Tensor Flow Lite for Microcontroller (TFLM) C++ Runtime Library12 lectures • 30min

ARM CMSIS-NN (Neural Network) Library6 lectures • 19min

Alif E7 Board For Embedded Based Machine Learning Use Cases9 lectures • 19min

Requirements

Description

Who this course is for: