Power contribution in the chip design is vital one for any chip design engineer who wants to implement low power is the cutting edge goal apart from the silicon scaling then this would be the best course to learn and advanced  topics covered in part2.  At deep submicron short channel all the time facing multiple design challenges along with silicon scaling. As the frequency of the design is achieving and the major implement gap while achieving frequency is area and power. In this course you are empowered to learn most of the low power techniques which practically uses in chip designing.

In this part 1 course covered introduction of the power consuming elements and its basic equations, CMOS current equation, different power dissipation in the design, power modes for robustness, power grid network, Power grid EM and IR, decaps in power network, active decap, decap distribution in power distribution network of micro processor, multi voltage, multi voltage power grid off and its low power methodology before power intent format from IEEE and implementation cells of power grid gating.

Power Performance Area are the three challenging sign off goals for any chip designer right from architecture to till GDSII Physical design engineer. All the design duration low power techniques are implemented.

Power contribution in entire SOC

•Power Grid Network

•Devices

•RC Network

•Data/Signal

•Clock

•Physical Only Cells

Present trending methodologies are covered in part-2 which is even more advanced way.