Zynq Ultrascale+MPSoC Development
2.7 (30 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
462 students enrolled

Zynq Ultrascale+MPSoC Development

Zynq Ultrascale+MPSoC Training with VIVADO IPI, SDK, Petalinux
2.7 (30 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
462 students enrolled
Created by Digitronix Nepal
Last updated 7/2020
Current price: $86.99 Original price: $124.99 Discount: 30% off
5 hours left at this price!
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This course includes
  • 2.5 hours on-demand video
  • 8 articles
  • 1 downloadable resource
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
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What you'll learn
  • Learn Zynq Ultrascale+ FPGA Design Methodology
  • Zynq Ultrascale+ MPSoC FPGA Design with VIVADO IPI, SDK and Petalinux
  • Create embedded systems with APU, RPU and GPU of the Zynq Ultrascale+MPSoC
  • Building Software Subsystems with VIVADO SDK and Petalinux
  • Create Bootable systems and Debugging the Software Application
  • Implement the MPSoC based projects on Ultra96 [ZCU100] FPGA Board
  • Idea of Zynq 7000 architecture
  • VIVADO Design Suit Overview
  • Basic Idea of SDSoC
  • Basic Idea of Embedded C/C++
  • Idea of Linux File system and Development

This course is on FPGA Development with Zynq Ultrascale+ FPGA Family, Programming different blocks of MPSoC. We have included sessions on Zynq Ultrascale+ FPGA  for  embedded processing , building bare-metal application, FSBL and custom bootable system.

This Course will widen your views on FPGA Development with Zynq Ultrascale+ MPSoC , VIVADO IPI, SDK, Petalinux and SDSoC (Software Defined System on Chip) Design Tools. We have sessions on Architecture of this family of FPGA and Design Flow to real time project with MPSoC and design tools. We also have some demonstration session of the MPSoC project on Ultra96[ZCU100] FPGA board.

Who this course is for:
  • FPGA engineer working on Embedded Design with Zynq MPSoC
  • Electrical Engineer
  • Electronics and Computer Engineering
  • Computer Science
Course content
Expand all 20 lectures 02:47:17
+ Section 1 Zynq Ultrascale+ Architecture Overview
4 lectures 46:35

Architecture details of Zynq Ultrascale+MPSoC, which includes Quad Core ARM Cortex A53-APU, Dual Core ARM Cortex R5 RPU, ARM Mali 400 GPU and Platofrm Management Unit. This Zynq Ultrascale+MPSoC has 3 device family: CG, EG, EV Devices among which EV has ARM Mali GPU and Video Codec. All Zynq Ultrascale+MPSoC consists of Ultrascale+ FPGA Core and High Speed Interface as PCIe. 

Preview 18:34

This is Part II of Zynq Ultrascale+ MPSoC architecture, Design Tools, Development Boards and Applications.

Zynq Ultrascale+MPSoC Architecture Part II

In this basic IP overview session, we have showed up the IP of Zynq Ultrascale+MPSoC Processing System IP in VIVADO 2017.4, How to configure it as our requirement in brief.

Section 1 Lab 1: Basic IP Overview and Customization

The first Boot up and GPIO control session with Avnet Ultra96 [Zynq Ultrscale+ MPSoC] FPGA.

Preview 03:58
+ Section 2 Basic Embedded Design with Zynq Ultrascale+ FPGA
5 lectures 01:12:49

This Section/Lecture is on How to create basic Embedded Application with Zynq Ultrascale+MPSoC, we have showed up the methodology for creating basic embedded application with APU or RPU.

Section 2 Basic Embedded Design with Zynq Ultrascale+MPSoC

In this lab session we are going to customize Zynq Ultrascale+MPSoC Processing System IP in VIVADO 2017.4, we will configure this IP with APU, RPU along with Memory, GPIO and SWDT. After configuration we will generate it's output products and Export those output products to SDK and Launch SDK.

Section 2 Lab 21_Embedded Design with Zynq Ultrascale_MPSoC

In this section we are going to write the application for APU (ARM Cortex A53) with SDK, we are going to generate Hello World Application for this APU from Default template of SDK. We will also setup the Debug Configuration and target it to the APU of Zynq Ultrascale+MPSoC.

Section 2 Lab 22 Creating Hello World Application for ARM Cortex A53

In this lab we are going to create Hello World application with VIVADO SDK for RPU (ARM Cortex R5) of Zynq Ultrascale+MPSoC. We will setup the Serial Terminal on the SDK and Test the Hello World project on RPU.

Section 2 Lab 23 Creating Hello World Application for Cortex R5

This is Hello World and Peripheral Test application project design with Xilinx VIVADO and implementing it on Ultra96 FPGA Board. Ultra96 is low cost Zynq Ultrascale+ MPSoC FPGA Board.

Lab 24: Hello World & Peripheral Test with VIVADO & Ultra96
+ Section 3 Building Software for PS Subsystem with VIVADO SDK and Petalinux
3 lectures 38:23

This Section is on what are the possibilities for creating software for PS subsystems (APU, RPU, GPU and PMU). How to create FSBL, Baremetal Application with SDK and How to create application (Uboot and DTB) with Petalinux 2017.4 System.

Section 3 Building Software for PS Subsystem with VIVADO SDK & Petalinux

This lab 31a and 31b is on creating First Stage Bootloader for ARM Cortex A53-APU and R5-RPU of the Zynq Ultrascale+MPSoC Processing System. We will create " Zynq MP FSBL" project for APU and RPU.

Section 3 Lab 31 a & Lab 31 b Creating FSBL for ARM Cortex A53 & R5

This lab is on Creating Baremetal Application (using FSBL and Hello World Application) for ARM Cortex A53-APU and R5-RPU of the Processing System.

Section 3 Lab 31c & Lab 31d Creating Baremetal Application for APU & RPU
+ Section 3 Part II: Petalinux Development with Zynq
1 lecture 01:08

Learn about the development methodology of Petalinux applications...

Petalinux Development Basics
+ FreeRTOS Development with MPSoC FPGA
1 lecture 01:49

This is session on how to create FreeRTOS application with multi-threading concept!

Lab: Creating Multi-thread application on FreeRTOS for MPSoC Boards: Ultra96
+ Machine Learning with MPSoC FPGA
4 lectures 04:17

This session is on implementing the "DPU TRD on Ultra96" this lecture is inspired from the "DPU Integration Tutorial" github project of Xilinx.

Deep Learning (DPU) TRD for Ultra96 FPGA

This article cover up the process of implementing resnet 50 with VIVADO/Petalinux 2019.2. This article is answer record from Xilinx.

ResNet-50 CNN implementation with VIVADO/Petalinux 2019.2 for Ultra96

In this lecture you will know about the process or building the "DPU TRD based on DNNDK for ZCU104". This session is inspired from the PG338 [DPU TRD guide for ZCU102] and UG1327 [DNNDK User guide].

DPU TRD for ZCU104 FPGA Board

This article explains on how to create DPU TRD for ZCU106 FPGA Board, which is MPSoC FPGA Board.

DPU (3.0) TRD for ZCU106
+ DPU-PYNQ Implementation on Ultra96/ZCU104/ZCU111
1 lecture 01:40

This session is on "highlighting the DPU-PYNQ" implementation process!

Deep Learning with DPU and PYNQ
+ Bonus Lecture
1 lecture 00:32

This Session includes the "Next after this course", How to explore with this course and tutorials and some Ultra Low Cost Code.

What Next?