Zynq Ultrascale+MPSoC Development
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- Learn Zynq Ultrascale+ FPGA Design Methodology
- Zynq Ultrascale+ MPSoC FPGA Design with VIVADO IPI, SDK and Petalinux
- Create embedded systems with APU, RPU and GPU of the Zynq Ultrascale+MPSoC
- Building Software Subsystems with VIVADO SDK and Petalinux
- Create Bootable systems and Debugging the Software Application
- Implement the MPSoC based projects on Ultra96 [ZCU100] FPGA Board
- Idea of Zynq 7000 architecture
- VIVADO Design Suit Overview
- Basic Idea of SDSoC
- Basic Idea of Embedded C/C++
- Idea of Linux File system and Development
This course is on FPGA Development with Zynq Ultrascale+ FPGA Family, Programming different blocks of MPSoC. We have included sessions on Zynq Ultrascale+ FPGA for embedded processing , building bare-metal application, FSBL and custom bootable system.
This Course will widen your views on FPGA Development with Zynq Ultrascale+ MPSoC , VIVADO IPI, SDK, Petalinux and SDSoC (Software Defined System on Chip) Design Tools. We have sessions on Architecture of this family of FPGA and Design Flow to real time project with MPSoC and design tools. We also have some demonstration session of the MPSoC project on Ultra96[ZCU100] FPGA board.
- FPGA engineer working on Embedded Design with Zynq MPSoC
- Electrical Engineer
- Electronics and Computer Engineering
- Computer Science
Architecture details of Zynq Ultrascale+MPSoC, which includes Quad Core ARM Cortex A53-APU, Dual Core ARM Cortex R5 RPU, ARM Mali 400 GPU and Platofrm Management Unit. This Zynq Ultrascale+MPSoC has 3 device family: CG, EG, EV Devices among which EV has ARM Mali GPU and Video Codec. All Zynq Ultrascale+MPSoC consists of Ultrascale+ FPGA Core and High Speed Interface as PCIe.
The first Boot up and GPIO control session with Avnet Ultra96 [Zynq Ultrscale+ MPSoC] FPGA.
In this lab session we are going to customize Zynq Ultrascale+MPSoC Processing System IP in VIVADO 2017.4, we will configure this IP with APU, RPU along with Memory, GPIO and SWDT. After configuration we will generate it's output products and Export those output products to SDK and Launch SDK.
In this section we are going to write the application for APU (ARM Cortex A53) with SDK, we are going to generate Hello World Application for this APU from Default template of SDK. We will also setup the Debug Configuration and target it to the APU of Zynq Ultrascale+MPSoC.
This Section is on what are the possibilities for creating software for PS subsystems (APU, RPU, GPU and PMU). How to create FSBL, Baremetal Application with SDK and How to create application (Uboot and DTB) with Petalinux 2017.4 System.