Zynq Ultrascale+MPSoC Development

Name: Zynq Ultrascale+MPSoC Development
Rating: 3.1 (74 reviews)

Zynq Ultrascale+MPSoC Training with VIVADO IPI, SDK, Petalinux

Created byDigitronix Nepal

Last updated 11/2022

English

What you'll learn

Learn Zynq Ultrascale+ FPGA Design Methodology
Zynq Ultrascale+ MPSoC FPGA Design with VIVADO IPI, SDK and Petalinux
Create embedded systems with APU, RPU and GPU of the Zynq Ultrascale+MPSoC
Building Software Subsystems with VIVADO SDK and Petalinux
Create Bootable systems and Debugging the Software Application
Implement the MPSoC based projects on Ultra96 [ZCU100] FPGA Board

Course content

9 sections • 21 lectures • 2h 47m total length

Zynq Ultrascale+MPSoC Architecture Part I18:34
Architecture details of Zynq Ultrascale+MPSoC, which includes Quad Core ARM Cortex A53-APU, Dual Core ARM Cortex R5 RPU, ARM Mali 400 GPU and Platofrm Management Unit. This Zynq Ultrascale+MPSoC has 3 device family: CG, EG, EV Devices among which EV has ARM Mali GPU and Video Codec. All Zynq Ultrascale+MPSoC consists of Ultrascale+ FPGA Core and High Speed Interface as PCIe.
Zynq Ultrascale+MPSoC Architecture Part II14:15
This is Part II of Zynq Ultrascale+ MPSoC architecture, Design Tools, Development Boards and Applications.
Section 1 Lab 1: Basic IP Overview and Customization9:48
In this basic IP overview session, we have showed up the IP of Zynq Ultrascale+MPSoC Processing System IP in VIVADO 2017.4, How to configure it as our requirement in brief.
Section 1 Lab 2: First Boot-Up of Ultra 96 FPGA [Zynq Ultrascale+ MPSoC]3:58
The first Boot up and GPIO control session with Avnet Ultra96 [Zynq Ultrscale+ MPSoC] FPGA.

Section 2 Basic Embedded Design with Zynq Ultrascale+MPSoC15:56
This Section/Lecture is on How to create basic Embedded Application with Zynq Ultrascale+MPSoC, we have showed up the methodology for creating basic embedded application with APU or RPU.
Section 2 Lab 21_Embedded Design with Zynq Ultrascale_MPSoC20:24
In this lab session we are going to customize Zynq Ultrascale+MPSoC Processing System IP in VIVADO 2017.4, we will configure this IP with APU, RPU along with Memory, GPIO and SWDT. After configuration we will generate it's output products and Export those output products to SDK and Launch SDK.
Section 2 Lab 22 Creating Hello World Application for ARM Cortex A5314:48
In this section we are going to write the application for APU (ARM Cortex A53) with SDK, we are going to generate Hello World Application for this APU from Default template of SDK. We will also setup the Debug Configuration and target it to the APU of Zynq Ultrascale+MPSoC.
Section 2 Lab 23 Creating Hello World Application for Cortex R54:30
In this lab we are going to create Hello World application with VIVADO SDK for RPU (ARM Cortex R5) of Zynq Ultrascale+MPSoC. We will setup the Serial Terminal on the SDK and Test the Hello World project on RPU.
Lab 24: Hello World & Peripheral Test with VIVADO & Ultra9617:11
This is Hello World and Peripheral Test application project design with Xilinx VIVADO and implementing it on Ultra96 FPGA Board. Ultra96 is low cost Zynq Ultrascale+ MPSoC FPGA Board.

Section 3 Building Software for PS Subsystem with VIVADO SDK & Petalinux11:04
This Section is on what are the possibilities for creating software for PS subsystems (APU, RPU, GPU and PMU). How to create FSBL, Baremetal Application with SDK and How to create application (Uboot and DTB) with Petalinux 2017.4 System.
Section 3 Lab 31 a & Lab 31 b Creating FSBL for ARM Cortex A53 & R514:21
This lab 31a and 31b is on creating First Stage Bootloader for ARM Cortex A53-APU and R5-RPU of the Zynq Ultrascale+MPSoC Processing System. We will create " Zynq MP FSBL" project for APU and RPU.
Section 3 Lab 31c & Lab 31d Creating Baremetal Application for APU & RPU12:58
This lab is on Creating Baremetal Application (using FSBL and Hello World Application) for ARM Cortex A53-APU and R5-RPU of the Processing System.

Deep Learning (DPU) TRD for Ultra96 FPGA0:26
This session is on implementing the "DPU TRD on Ultra96" this lecture is inspired from the "DPU Integration Tutorial" github project of Xilinx.
ResNet-50 CNN implementation with VIVADO/Petalinux 2019.2 for Ultra960:33
This article cover up the process of implementing resnet 50 with VIVADO/Petalinux 2019.2. This article is answer record from Xilinx.
DPU TRD for ZCU104 FPGA Board0:21
In this lecture you will know about the process or building the "DPU TRD based on DNNDK for ZCU104". This session is inspired from the PG338 [DPU TRD guide for ZCU102] and UG1327 [DNNDK User guide].
DPU (3.0) TRD for ZCU1062:56
This article explains on how to create DPU TRD for ZCU106 FPGA Board, which is MPSoC FPGA Board.

Requirements

Idea of Zynq 7000 architecture
VIVADO Design Suit Overview
Basic Idea of SDSoC
Basic Idea of Embedded C/C++
Idea of Linux File system and Development

Description

This course is on FPGA Development with Zynq Ultrascale+ FPGA Family, Programming different blocks of MPSoC. We have included sessions on Zynq Ultrascale+ FPGA for embedded processing , building bare-metal application, FSBL and custom bootable system.

This Course will widen your views on FPGA Development with Zynq Ultrascale+ MPSoC , VIVADO IPI, SDK, Petalinux and SDSoC (Software Defined System on Chip) Design Tools. We have sessions on Architecture of this family of FPGA and Design Flow to real time project with MPSoC and design tools. We also have some demonstration session of the MPSoC project on Ultra96[ZCU100] FPGA board.

Who this course is for:

FPGA engineer working on Embedded Design with Zynq MPSoC
Electrical Engineer
Electronics and Computer Engineering
Computer Science

Zynq Ultrascale+MPSoC Development

What you'll learn

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Course content

Section 1 Zynq Ultrascale+ Architecture Overview4 lectures • 47min

Section 2 Basic Embedded Design with Zynq Ultrascale+ FPGA5 lectures • 1hr 13min

Section 3 Building Software for PS Subsystem with VIVADO SDK and Petalinux3 lectures • 38min

Section 3 Part II: Petalinux Development with Zynq1 lecture • 1min

FreeRTOS Development with MPSoC FPGA1 lecture • 2min

Machine Learning with MPSoC FPGA4 lectures • 4min

MPSoC-DPU TRD VIVADO Flow (Vitis AI 2.0)1 lecture • 1min

DPU-PYNQ Implementation on Ultra96/ZCU104/ZCU1111 lecture • 2min

Bonus Lecture1 lecture • 1min

Requirements

Description

Who this course is for: