Learn Vivado from Top to Bottom - Your Complete Guide
- 4 hours on-demand video
- 12 articles
- 11 downloadable resources
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- Use Vivado confidently and proficiently.
- Understand the steps required to take their FPGA design from start to finish.
- Implement a micro blaze softcore processor on their FPGA.
- Generate HDL designs from c based code, using Vivado’s high level synthesis tool.
- Download and install Xilinx’s Vivado Design Suite, we will cover how to do this is the course if you are unsure of how to do so.
- Understand or familiar with what an FPGA is and how they operate.
- Interested in FPGA development and design.
The Vivado design suite is the set of tools provided by Xilinx and is used to design, program, and debug Xilinx’s line of FPGAs. This course covers all of the different aspects and capabilities of the Vivado design suite. This course covers everything from the very basics to the more complex topics. This course is designed so that the student who has no experience with Vivado can take the course by starting with the very basics topics such as creating projects and design files. There are also more advanced topics so that the experienced student can learn things like how to create and program a soft core processor using the tools provided by Xilinx. This course covers many topics, including:
- Downloading & Installing Vivado (I will be using a Windows machine, however you can install this on a Linux machine as well)
- Creating Projects
- Simulating Your Hardware Designs
- Using Existing IP Cores
- Creating & Managing Your Custom IP Cores
- Creating and Programming a Micro Blaze soft core processor
- Programming your Development Board
- Automating Vivado Using Tool Command Line (tcl) Scripts
- Creating Your Own Design Constraints
- Converting Your C Code to a Hardware Design
Vivado contains many tools and this course will cover all of them, including:
- Vivado's Hardware Manager - This is used to load the hardware designs onto the FPGA or on board memory.
- Vivado's Simulator - This is what is used to simulate and verify that your design is working as expected.
- Integrated Logic Analyzer (ILA)- This is used to act as a virtual oscilloscope while your design is running on the actual hardware target.
- Vivado's High Level Synthesis - This tool read C based code and converts it to a HDL based design.
- Xilinx's Software Development Kit (SDK) - This is the tool used to write C code that will run on the soft core processor implemented on the FPGA.
This course is laid out in such a way that each section takes on a specific topic or tool associated with Vivado. There are downloadable files that will have the students interact with Vivado so that they can get a hands on learning experience. The students will complete a hardware design project that will take them through all of the design steps neccasary so that they can start implementing their own idea's on Xilinx FPGAs using Vivado Design Suite. Vivado is a very powerful tool that has a lot to offer and this course is designed to help aid you in learning how to use this powerful tool.
- Anyone who works with Xilinx’s FPGAs.
- Anyone who has an interest in understanding the tools used to implement designs on Xilinx FPGAs.
- Altera based designers who would like to migrate to Xilinx based designs.
- Makers who want to get started with FPGA development.
- Students who are taking a course that requires FPGA design or development.
This lecture introduces the course and explains everything that will be covered. This lecture also explains the course layout and what you can expect from this course.
In this lecture you will see step-by-step how to download and install the Vivado design suite on your computer.
This lecture explains what you will see when you open Vivado for the first time.
This lecture will walk you through step-by-step on how to create a RTL project in Vivado. RTL projects are what we use to create designs we want to implement on the FPGA.
This lecture will walk you through how to add existing design files to your project. This is useful if you are developing the design in a separate program or received a design from someone else.
There are several ways to create a project in Vivado, the most straightforward being to use the new project wizard. However, if you are creating a lot of projects and they all are using the same parts / settings then creating a custom TCL will save a lot of time. In this lecture you will be shown step-by-step how to use TCL scripts to create a Vivado Project.
When working with revision control software its ideal to have the smallest file sizes possible. Instead of checking in entire projects and generated files, it’s possible to only check in TCL scripts and source files. This lecture will show you how to generate a TCL script that will re-generate your project and block design.
This lectures shows ways to manipulate the simulated waveform for analysis. There are step-by-steps showing how to do the following:
- Zooming in/out or to a specific region
- Measuring time between signal edges
- Adding waves to the window
- Saving a waveform configuration file
- Change the format of a signal (radix)
While your troubleshooting / simulating your design using Vivado’s simulator you may need to generate inputs without having to modify the test bench. This lecture shows how to force an input or internal signal to a specified value to help aid in the debugging process.
This lecture explains the different tools provided in the Vivado Tool Suite that are available to help you debug and verify that your design is working properly. Debugging hardware design is extremely challenging, but Vivado has some very powerful tools available to help you test and verify your design.
The Integrated Logic Analyzer Core is a logic analyzer that resides in your FPGA design while running. This core has many capabilities that an external logic analyzer would contain as well. In this lecture I am going to show you how to use the ILA debugging core.
The virtual I/O core is very useful for debugging designs; it can be used to see what is happening while your design is running. This is very useful because there are occasions when your simulation works but your design does not. In this lecture I am going to show you how to use the VIO debugging core.