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IT & Software Hardware Vivado

Learn Vivado from Top to Bottom - Your Complete Guide

The complete guide for implementing designs on Xilinx FPGAs using Vivado Design Suite, for beginners and advanced users
Bestseller
Rating: 4.5 out of 54.5 (684 ratings)
3,151 students
Created by Jordan Christman
Last updated 1/2017
English
English [Auto]
30-Day Money-Back Guarantee

What you'll learn

  • Use Vivado confidently and proficiently.
  • Understand the steps required to take their FPGA design from start to finish.
  • Implement a micro blaze softcore processor on their FPGA.
  • Generate HDL designs from c based code, using Vivado’s high level synthesis tool.

Requirements

  • Download and install Xilinx’s Vivado Design Suite, we will cover how to do this is the course if you are unsure of how to do so.
  • Understand or familiar with what an FPGA is and how they operate.
  • Interested in FPGA development and design.
  • A desire to learn about how to use XIlinx's development tool

Description

The Vivado design suite is the set of tools provided by Xilinx and is used to design, program, and debug Xilinx’s line of FPGAs. This course covers all of the different aspects and capabilities of the Vivado design suite. This course covers everything from the very basics to the more complex topics. This course is designed so that the student who has no experience with Vivado can take the course by starting with the very basics topics such as creating projects and design files. There are also more advanced topics so that the experienced student can learn things like how to create and program a soft core processor using the tools provided by Xilinx. This course covers many topics, including:

  • Downloading & Installing Vivado (I will be using a Windows machine, however you can install this on a Linux machine as well)
  • Creating Projects
  • Simulating Your Hardware Designs
  • Using Existing IP Cores
  • Creating & Managing Your Custom IP Cores
  • Creating and Programming a Micro Blaze soft core processor
  • Programming your Development Board
  • Automating Vivado Using Tool Command Line (tcl) Scripts
  • Creating Your Own Design Constraints
  • Converting Your C Code to a Hardware Design

Vivado contains many tools and this course will cover all of them, including:

  • Vivado's Hardware Manager - This is used to load the hardware designs onto the FPGA or on board memory.
  • Vivado's Simulator - This is what is used to simulate and verify that your design is working as expected.
  • Integrated Logic Analyzer (ILA)- This is used to act as a virtual oscilloscope while your design is running on the actual hardware target.
  • Vivado's High Level Synthesis - This tool read C based code and converts it to a HDL based design.
  • Xilinx's Software Development Kit (SDK) - This is the tool used to write C code that will run on the soft core processor implemented on the FPGA.

This course is laid out in such a way that each section takes on a specific topic or tool associated with Vivado. There are downloadable files that will have the students interact with Vivado so that they can get a hands on learning experience. The students will complete a hardware design project that will take them through all of the design steps neccasary so that they can start implementing their own idea's on Xilinx FPGAs using Vivado Design Suite. Vivado is a very powerful tool that has a lot to offer and this course is designed to help aid you in learning how to use this powerful tool.

Who this course is for:

  • Anyone who works with Xilinx’s FPGAs.
  • Anyone who has an interest in understanding the tools used to implement designs on Xilinx FPGAs.
  • Altera based designers who would like to migrate to Xilinx based designs.
  • Makers who want to get started with FPGA development.
  • Students who are taking a course that requires FPGA design or development.

Featured review

Vikas Mishra
Vikas Mishra
49 courses
6 reviews
Rating: 5.0 out of 511 months ago
The course is very informative and help to understand the Xilinix Vivado tool. I will definitely recommend every beginner to take up this course if you want to spend less time in understanding the tool rather than actual development.

Course content

13 sections • 70 lectures • 4h 26m total length

  • Preview02:00
  • Introduction to the Vivado Tool Suite
    01:49
  • Preview07:17
  • Supported FPGAs and Development Boards
    01:48

  • Preview02:50
  • Preview02:24
  • Importing a Xilinx ISE Project Into Vivado
    03:52
  • Create a Project From a Predefined Template
    02:34
  • Vivado Example Project
    04:29
  • Preview03:00
  • Creating New Files
    04:10
  • Working with Block Designs in Vivado
    06:04
  • Generating the FPGA Configuration File
    03:45
  • Programming Your Development Board
    02:19
  • Documentation Navigator
    01:47

  • I/O Pin Planning Tool Introduction
    01:55
  • Create an I/O Pin Planning Project
    02:21
  • Create and Place I/O Ports
    04:53
  • Perform a Design Rules Check
    01:35
  • Report Simultaneous Switching Noise SSN
    03:29
  • Generate Contraints File and Top Level HDL File
    04:16

  • Introduction to IP Cores
    04:04
  • Using IP Cores
    02:55
  • Create IP Cores from a Specific Directory
    06:45
  • Create IP Cores from a Block Design
    06:28
  • AXI Interface Explained
    05:10
  • Create an AXI IP Core Peripheral Step 1
    02:54
  • Creating an AXI IP Core Peripheral - Step 2
    10:36
  • Create an AXI IP Core Peripheral Step 3
    06:43
  • Customizing IP Cores
    02:45
  • Creating a Custom IP Core Repository
    00:36
  • IP Core Repository Directory Structure
    00:40
  • Adding IP Cores to Your Repository
    04:06
  • Adding a Custom IP Core Repository to a Vivado Project
    02:08
  • Managing a Custom IP Core Repository
    04:54

  • Configure Internal FPGA Block RAM (BRAM)
    04:36
  • Xilinx Memory Interface Generator (MIG) IP Core
    07:03
  • Connecting Multiple AXI Peripherals to a Single Master
    02:44
  • Using Vivado's Connection Automation and Regerating Block Design Layouts
    03:32

  • What are Design Constraints
    01:05
  • Applying I/O Constraints
    03:15
  • Creating Clock Constraints
    03:16

  • TCL Script Introduction
    02:55
  • Build a Vivado Project Using TCL Scripts
    03:32
  • Populate a Block Design Using TCL Scripts
    01:16
  • Using TCL Scripts in Your Custom IP Core
    03:17
  • How to Create Your Own Custom TCL Scripts
    03:22

  • Creating Simulation Files (Test Benches)
    03:29
  • Simulating Your Designs in Vivado
    04:01
  • Modifying the Simulation Waveform
    07:06
  • Forcing Signal Values for Simulation
    03:40
  • Vivado Debugging Tools Introduction
    02:47
  • How to Use the Integrated Logic Analyzer (ILA) Core for Debugging
    09:01
  • How to Use the Virtual I/O (VIO) Core for Debugging
    07:28

  • Creating Your First Softcore Processor Project
    05:27
  • Add AXI Peripherals to Your MicroBlaze Processor
    05:39

  • High Level Synthesis Tool Introduction
    02:48

Instructor

Jordan Christman
FPGA * VHDL * MATLAB Enthusiast
Jordan Christman
  • 4.2 Instructor Rating
  • 6,666 Reviews
  • 46,835 Students
  • 15 Courses

        A graduate from the University of Dayton with his Bachelor's degree in Electronic and Computer Engineering Technology. He also graduated from UD with his Master's degree in Electrical Engineering. He currently has a patent pending for an electronic monitoring device. He has strong knowledge in FPGA (Field Programmable Gate Array) development, Digital Electronics, Circuit Board design, and VHDL design and modeling of hardware systems. His focus of study in school was embedded systems which involves circuit design, firmware development, implementation of computer hardware, and the interfacing of computer operating systems. His hobbies include mobile application development, layout and assembly of PCB's (Printed Circuit Boards), computer application programming, and anything related to electrical engineering. 

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