VHDL for FPGA: Learn from Scratch to Mastery

Explore the basic structure of VHDL code, including the entity with ports, architecture, libraries, signals, components, processes, and the begin section.

Explore FPGA port modes, including input, output, inout, and buffer ports, and learn how pins, buffers, and internal gates enable reading or driving data.

Explore VHDL data types for FPGAs, focusing on std_logic, std_logic_vector, unsigned, signed, and packages. Understand how signal sizes, space, and timing affect hardware designs.

Learn how to define and use arrays and records in VHDL for FPGA, including declaring types with ranges, array and memory usage, and the differences between arrays and records.

learn how to declare and use signals, variables, and constants in VHDL for FPGA design, differentiate between simulation and synthesis, and assign values inside processes.

Explore VHDL operators for FPGA, including logical, relational, and arithmetic operators, plus shift and rotate operations on bit vectors with practical examples.

Explore VHDL attributes, including high, low, base, and length, and learn how to use clock edge and event properties with subtypes and arrays.

Learn to create an alias for a full or partial array range in VHDL, using signals or variables, with subranges like 31 downto 28.

Explore the entity as the basic design unit, a black box with inputs and outputs, and see how top entities host components, ports, and architecture in VHDL for FPGA.

Explore VHDL architecture as the running description of a design entity, where flip-flops and logic reside inside the code.

Explore component instantiation as a concurrent statement to connect circuit elements and build large architectures in VHDL. Declare components, map ports, and wire signals across a top entity.

Explore how the VHDL process works as a concurrent statement with sequential statements and a sensitivity list. Distinguish clocked versus combinational processes, line-by-line execution, and resets in examples.

Learn how to use libraries and packages in VHDL, write library and use statements, explore IEEE standard and vendor libraries, and share constants and variables across files with packages.

Discover how generics in VHDL pass static data into an entity, how to declare them and map with generic maps, and when extra design units are used.

Learn functions and procedures in vhdl, where functions return a single value with combinational behavior, and procedures return multiple outputs and execute reusable code across architecture, process, or package.

Explore blocks in VHDL, including simple and guarded blocks, learn that guarded blocks simulate but are not synthesized, and why blocks are generally discouraged in FPGA design.

Discover how VHDL packages and package bodies organize constants, variables, types, and components, with header-like declarations and libraries to share across designs, and how to implement and call package bodies.

Explore VHDL configurations, linking a design entity to a chosen architecture to assign a component’s architecture, typically for simulation rather than synthesis.

Explore VHDL declaration statements, defining constants, types, signals, variables, components, and subprograms within architecture, with emphasis on scope, order, and practical examples.

Explore concurrent statements in VHDL, understand that order doesn't matter for concurrency, and learn how signal assignments, component instantiations, and processes differ in behavior and synthesis.

Learn about concurrent statements in VHDL by exploring signal assignment options: regular assignments, when-else, and the select form called witzelsucht.

Explore generate statements to replicate concurrent components using for and if constructs, and connect to ports with generics to build a counter and vectors.

Explore sequential statements inside a process to describe both combinational and sequential logic, using signal and variable declaration, assignments, if or case, loops, and wait statements.

Learn to use if statements as sequential constructs inside a VHDL process, including else and else if branches, and the importance of describing all conditions to avoid synthesis timing issues.

Explore the case statement within a process to implement sequential logic, cover all options with case others, and build state machines using ordered case branches.

Demonstrate for loop usage in VHDL, including exit and next to control iterations, within a process. Show how a 127 down to 0 vector becomes zeroed as logic during synthesis.

Discover how while loops function in VHDL for FPGA, why infinite while true loops aren’t synthesizable, and implement bounded loops with a counter in simulations or test benches.

Explore sequential statements in VHDL by using the wait statement to pause a process until a condition or clock event occurs, including time delays like 10 nanoseconds and rising edges.

Create a flip-flop in VHDL for FPGA using a clocked process with a sensitivity list, capturing D at the rising edge into Q.

Understand latches and latch gates, why unintended latch behavior occurs in asynchronous processes, and how to avoid it with a clock and sensitivity lists.

Explores asynchronous and synchronous resets in VHDL, explaining how to synchronize resets to the clock, use sensitivity lists, avoid glitches, and manage timing and noise in FPGA design.

Explore how variable and signal behave inside a clocked process in VHDL for FPGA, highlighting immediate versus clock-delayed updates with a 0–5 counter example.

Explore Moore state machines and contrast them with Mealy machines, showing design with case statements, reset initialization, and safety via others in a communication protocol example.

Explore the mealy state machine and how its output depends on input and state, then examine how noise can create unwanted states, with a fix promised in the next lecture.

Master one hot enumeration for state machines in VHDL, comparing one hot encoding to binary and reducing risky state jumps. Learn how synthesizers assign initial states and ensure safer transitions.

learn how to implement a simple and gate in vhdl for fpga, including writing an entity and architecture with two inputs and one output, compare a direct and gate assignment with a conditional implementation, and simulate with modelsim.

Implement an N-bit up counter in vhdl for fpga, with clock, synchronous reset, a count enable input, and an output q vector of N bits that counts zero to end-1.

Learn to simulate an 8-bit VHDL counter for FPGA with ModelSim, build a test bench, and validate the top entity using clock and reset signals.

Design an eight-bit shift-left register in VHDL for FPGA that loads data on a load signal, shifts left on a shift enable, and outputs the result with clock and reset.

Design a single ram memory in an FPGA with VHDL, modeling memory as an array of vectors with width and depth, including data in, data out, and read/write enables.

Design a 10-microsecond delay component in VHDL for an FPGA using a 10 MHz clock and a counter with a done flag to feed a traffic light state machine.

Design a traffic light state machine in VHDL using a delay component to manage red, yellow, and green phases, with an active-low reset and clock-driven transitions.

Run and verify a traffic light state machine with a VHDL simulation using a test bench, a 10 megahertz clock, and a counter. Debug delays and waveform outputs.

Run the traffic-light FPGA design on a real Avnet Minisub board. Load the bitstream via QSPI memory and a data cable, and compare hardware behavior with simulation.

Use the integrated logic analyzer to debug an FPGA in real time, inspect the one-hot FSM and traffic-light outputs, and experiment with triggers and running synthesis.