Learn Verilog with Xilinx VIVADO Tool
3.7 (72 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
572 students enrolled

Learn Verilog with Xilinx VIVADO Tool

Learn Verilog Programming from top to bottom with Xilinx VIVADO Design Suite for FPGA Development
3.7 (72 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
572 students enrolled
Created by Digitronix Nepal
Last updated 9/2019
English
English [Auto]
Current price: $93.99 Original price: $134.99 Discount: 30% off
5 hours left at this price!
30-Day Money-Back Guarantee
This course includes
  • 4 hours on-demand video
  • 4 articles
  • 13 downloadable resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
Training 5 or more people?

Get your team access to 4,000+ top Udemy courses anytime, anywhere.

Try Udemy for Business
What you'll learn
  • Learn and understand about Verilog Programming Language
  • Verilog Design Flow and its Syntax/Semantics
  • Creating Basic Logic Gates in Verilog
  • VIVADO Design Flow for FPGA Design with Verilog
  • Understand Conditional Statement in Verilog
  • Combinational and Sequential Circuit Design with Verilog
  • Finite State Machine Design with Verilog
  • Structural Modeling/Design with Verilog
Requirements
  • Basics of Programming Language (C/C++ or any)
  • Basic Idea of Digital Design
  • We introduce Verilog from Very Basics so you don't need to Worry about Prerequisites!!!
Description

This Course is crash course on Verilog Programming from Top to Bottom with Xilinx VIVADO Design suite. Verilog is dominant Hardware Description Language on FPGA/ASIC/VLSI Design and Verification Market globally. It has more than 50% of market share in global market. So getting idea of Verilog programming will be the plus point in your Resume for Job Application.

In this course we have introduced Verilog Programming in very simple manner so beginner who don't have any idea can get Verilog HDL idea from scratch to intermediate level.

We have Sections on Introduction and Basic Design with Verilog Programming, Simulation with Verilog and Creating Verilog Testbench, Conditional Statement in Verilog, Combinational Circuit Design with Verilog, Sequential Circuit Design with Verilog, Finite State Machine (FSM) Design and Structural Modeling with Verilog. All the Sections have Lab sessions which will done on VIVADO Design Suite.

VIVADO is State of Art FPGA Design environment which have great features of Designing HDL Projects, Synthesizing, Implementing the HDL Project and Generating Bitstream as well as Configuring the Project on FPGA. VIVADO has awesome features on Design/Resources Optimization, Static Timing Analysis and Performance Optimization.

Who this course is for:
  • Electrical Engineering
  • Computer Science
  • FPGA Design Enthusiast
  • Computer Engineering
  • Electrical and Electronics Engineering
Course content
Expand all 19 lectures 04:33:35
+ Introduction and Basic Design with Verilog and VIVADO
4 lectures 58:17

This Section is introduction verilog, verilog syntax, verilog revisions and Verilog design flow. we have introduced all the components of verilog program i.e module declaration, port declaration, assignment operation and end module in this section.

Preview 19:56

This secction is continuation of previous section which consists of detail explanation of Module declaration, assign statement and port declaration in verilog. This lecture also consists of references/bibliography: books and links for verilog programming.

Preview 13:43

From this section you will know about how to download, install VIVADO and get 30 day evaluation license from xilinx.com.

VIVADO is state of art FPGA Design and Verification environment(IDE) which will allow you to design, test, verify and package your design for FPGA Market.

How to Download, Install VIVADO & Get 30 Day Evaluation License
04:51

This is first practical lab session in VIVADO Design suit, we have explained about the VIVADO GUI features, processes on VIVADO design environment. In this section we have created a very basic logic gate: and gate, we have created/viewed the RTL schematic and synthesized the Verilog program.

Section 1 Lab 1 Basic Logic Gate Design with VIVADO in Verilog
19:47
+ Simulation with Verilog Testbench
2 lectures 31:04

This section explains about the creating testbench on verilog, components of testbench: DUT, instantiation stimulus. We also have included how to create testbench for basic logic gate:AND Gate.

Section 2 Simulation with Verilog and Testbench Introduction
11:11

This is Lab session on Design and Simulation of AND Gate and then OR Gate. In this session we are going to design and create simulation testbench for AND gate and OR Gate. We have talk on how to write HDL code for Logic Gate and How to Create a Simulation testbench from scratch.

Section 2 Lab 1 Design Simulation of AND OR Gate
19:53
+ Section 3 Conditional Statement in Verilog
2 lectures 31:03

Conditional Statements are those statement which evaluates the condition, if the condition is true then expression_1 will executed else expression_2 will executed. There are different Conditional Statement in Verilog which are : "always block","if statement","case Statement". We also have talk on Looping structure in Verilog in this session.

Section 3 Conditional Statement in Verilog Overview
14:52

This Session is Lab on MUX(4:1) Design and Simulation in Verilog with VIVADO Design Suit. From this lab you will know about the Always Block , Case Statement and MUX Design as well as Creating Simulation Waveform for MUX.

Section 3 Lab 1 MUX 4:1 Design and Simulation
16:11
+ Section 4 Combinational Circuit Design with Verilog
1 lecture 20:22

This Section introduces the Combinational Circuit Overview, Types of Combinational Circuit and Designing and Simulating  Combinational Circuit in Verilog with VIVADO. In this Section there is lab session of Multiplexer Design and Simulation, Decoder Design and Simulation.

Section 4 Combinational Circuit Design with Verilog
20:22
+ Section 5 Sequential Circuit Design
1 lecture 20:23

This Lecture taught about the Sequential Circuit Design with Verilog, Overview of Sequential Circuits and Designing/simulating sequential circuit. We have explained about Latch, Flipflop, Register design in this session

Section 5 Sequential Circuit Design with Verilog
20:23
+ Section 6 Structural Design with Verilog
2 lectures 25:48

Structural Design basics has been introduced here, the Module Declaration, integration of different modules and port mapping has been explained in detail in this section.

Section 6 Structural Design with Verilog I
19:46

This section covers "how to design 4 bit Full Adder using 1 bit Full Adder (or just Adder) in details".

Section 6 Structural Design with Verilog II
06:02
+ 8 bit ALU Design and Simulation on Verilog with Xilinx VIVADO
1 lecture 01:23

How to Design and Simulate the 8 bit ALU on Xilinx VIVADO! Here is the Tutorial!

8 bit ALU Design and Simulation on Verilog with Xilinx VIVADO
01:23
+ Verilog Reference Guide (From Basics to Advance Verilog Design)
1 lecture 22:06

This Reference Guide is insightful document of Verilog Programming language from basic logic gates to the Signal Processing Examples.

Reference Guide of Verilog
22:06
+ Summary: Verilog Programming
3 lectures 01:02:00
Lexical Conventions in Verilog
18:24
Verilog Data Types, Directives and Dataflow Modeling
20:58
Procedural Assignments in Verilog
22:38
+ Conclusion
2 lectures 01:08

This is Bonus Lecture and What Next Session!

What Next?
00:35

Necessary Books and Reference Links

Books and Reference Links
00:33