Learn Verilog with Xilinx VIVADO Tool
- 4 hours on-demand video
- 4 articles
- 13 downloadable resources
- Full lifetime access
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- Certificate of Completion
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- Learn and understand about Verilog Programming Language
- Verilog Design Flow and its Syntax/Semantics
- Creating Basic Logic Gates in Verilog
- VIVADO Design Flow for FPGA Design with Verilog
- Understand Conditional Statement in Verilog
- Combinational and Sequential Circuit Design with Verilog
- Finite State Machine Design with Verilog
- Structural Modeling/Design with Verilog
- Basics of Programming Language (C/C++ or any)
- Basic Idea of Digital Design
- We introduce Verilog from Very Basics so you don't need to Worry about Prerequisites!!!
This Course is crash course on Verilog Programming from Top to Bottom with Xilinx VIVADO Design suite. Verilog is dominant Hardware Description Language on FPGA/ASIC/VLSI Design and Verification Market globally. It has more than 50% of market share in global market. So getting idea of Verilog programming will be the plus point in your Resume for Job Application.
In this course we have introduced Verilog Programming in very simple manner so beginner who don't have any idea can get Verilog HDL idea from scratch to intermediate level.
We have Sections on Introduction and Basic Design with Verilog Programming, Simulation with Verilog and Creating Verilog Testbench, Conditional Statement in Verilog, Combinational Circuit Design with Verilog, Sequential Circuit Design with Verilog, Finite State Machine (FSM) Design and Structural Modeling with Verilog. All the Sections have Lab sessions which will done on VIVADO Design Suite.
VIVADO is State of Art FPGA Design environment which have great features of Designing HDL Projects, Synthesizing, Implementing the HDL Project and Generating Bitstream as well as Configuring the Project on FPGA. VIVADO has awesome features on Design/Resources Optimization, Static Timing Analysis and Performance Optimization.
- Electrical Engineering
- Computer Science
- FPGA Design Enthusiast
- Computer Engineering
- Electrical and Electronics Engineering
This Section is introduction verilog, verilog syntax, verilog revisions and Verilog design flow. we have introduced all the components of verilog program i.e module declaration, port declaration, assignment operation and end module in this section.
This secction is continuation of previous section which consists of detail explanation of Module declaration, assign statement and port declaration in verilog. This lecture also consists of references/bibliography: books and links for verilog programming.
From this section you will know about how to download, install VIVADO and get 30 day evaluation license from xilinx.com.
VIVADO is state of art FPGA Design and Verification environment(IDE) which will allow you to design, test, verify and package your design for FPGA Market.
This is first practical lab session in VIVADO Design suit, we have explained about the VIVADO GUI features, processes on VIVADO design environment. In this section we have created a very basic logic gate: and gate, we have created/viewed the RTL schematic and synthesized the Verilog program.
This is Lab session on Design and Simulation of AND Gate and then OR Gate. In this session we are going to design and create simulation testbench for AND gate and OR Gate. We have talk on how to write HDL code for Logic Gate and How to Create a Simulation testbench from scratch.
Conditional Statements are those statement which evaluates the condition, if the condition is true then expression_1 will executed else expression_2 will executed. There are different Conditional Statement in Verilog which are : "always block","if statement","case Statement". We also have talk on Looping structure in Verilog in this session.
This Section introduces the Combinational Circuit Overview, Types of Combinational Circuit and Designing and Simulating Combinational Circuit in Verilog with VIVADO. In this Section there is lab session of Multiplexer Design and Simulation, Decoder Design and Simulation.