
Discover why hardware description languages matter and how HDL describes hardware behavior with Verilog or VHDL. Experience simulation, test benches, and parallel hardware design for FPGA and ASIC applications.
Use the online EDA playground to test Verilog HDL, sign up with a company or institution email, write a simple module with initial begin and $display, and run simulations.
Learn how to use the Verilog $display command in test benches to print time and signal values (A and B) in binary, with stepwise time intervals and formatting options.
Explain the difference between $display and $monitor in verilog, showing how $display prints on execution while $monitor updates on any variable change in a test bench.
Explore blocking vs non-blocking assignments in Verilog through hands-on examples, contrasting immediate versus clock-synchronized updates and their impact on sequential versus combinational logic.
Learn Verilog HDL from scratch with hands-on simulation by building a 4-bit adder in Verilog, testing it with a SystemVerilog test bench in the EDA Playground.
Learn to implement if else if else logic in Verilog with a grading system example. Build a test bench to simulate grading outcomes using $display and $time.
Learn Verilog HDL From Scratch with Hands-On Simulation
Want to learn Verilog in a practical and beginner-friendly way?
This course is designed for students, electronics enthusiasts, and aspiring digital design engineers who want to master Verilog Hardware Description Language (HDL) from the ground up using EDA Playground.
Unlike theory-heavy courses, this course focuses on hands-on learning through live coding demonstrations and simulations in every lecture. You will write, test, debug, and simulate Verilog code directly in your browser — no hardware, FPGA board, or software installation required.
You will start by understanding why HDL matters and how Verilog is used in modern digital systems, then gradually move toward practical circuit design and simulation.
What You’ll Learn
Verilog HDL fundamentals from scratch
Writing and simulating Verilog code
Understanding delays and arithmetic operations
Using system tasks like $display and $monitor
Blocking vs non-blocking assignments
Designing combinational and sequential logic
Building digital circuits like adders and multiplexers
Writing conditional statements in Verilog
Using testbenches and waveform analysis in simulation
Why Take This Course?
Beginner-friendly explanations
Practical coding in every lecture
Learn directly on EDA Playground
No FPGA hardware required
Step-by-step hands-on simulations
Ideal for university students and self-learners
Course Content
Introduction
Lecture 1: Why HDL Matters?
Lecture 2: Getting Started with Verilog: From Microcontrollers to FPGA Verilog
Setting Up Tools
Lecture 3: Getting Started with EDA Playground
Learning Verilog
Lecture 4: Delay in Verilog
Lecture 5: Arithmetic in Verilog
Lecture 6: $display Command in Verilog
Lecture 7: $monitor Command in Verilog
Lecture 8: $display vs $monitor in Verilog
Lecture 9: Blocking vs Non-Blocking Assignment in Verilog
Lecture 10: Combinational Logic in Verilog
Lecture 11: Sequential Logic in Verilog
Lecture 12: 4-Bit Adder Using Verilog
Lecture 13: Design and Simulate 2:1 MUX in Verilog
Lecture 14: Design and Simulate Half Adder in Verilog
Lecture 15: If-Else Conditional Statements in Verilog
Lecture 16: If-Else-If Statements in Verilog
Lecture 17: Case Statement in Verilog
Lecture 18: Opening Waveforms in EDA Playground Testbench Simulation
By the end of this course, you will have the confidence to write, simulate, and debug Verilog code and build a strong foundation for digital design, FPGA development, and advanced hardware design concepts.
Moreover, I keep on updating this course. More lectures will be added on the way. Stay tuned.