Learn SystemVerilog Assertions and Coverage Coding in-depth
Requirements
- Basic concepts in Verification
- A desire to learn important skills essential for a Functional Verification job
Description
A course that will help you learn everything about System Verilog Assertions (SVA) and Functional coverage coding which forms the basis for the Assertion based and Coverage Driven Verification methodologies. These are the two key methodologies used most widely in all current SOC/chip designs to ensure quality and completeness.
The course covers everything from concepts to coding along with several examples to illustrate as well as quizzes and lab exercises to make your learning thorough.
The course contents include several examples and illustrations from LRM and other popular books on SystemVerilog.
Who this course is for:
- Students of VLSI/Digital/Embedded design looking for a job in Front end VLSI design
- Professional Logic Design and Verification Engineers who wants to increase their skills
Instructor
- 4.5 Instructor Rating
- 10,648 Reviews
- 73,091 Students
- 4 Courses
Experienced and Passionate Verification Engineer with 18+ years of experience in design verification of complex Microprocessors, ASIC and SOC designs at major semiconductor companies like Intel, IBM and other exciting startups.
Co-Author of book "Cracking Digital VLSI Verification Interviews: Interview Success" available on Amazon
Passionate in continuous learning of new and interesting technologies and always ready to share knowledge and help others
Quora Top Writer 2017 ,2018 in VLSI/Semiconductor topics