Learn to build OVM & UVM Testbenches from scratch
Requirements
- Basic understanding of Functional Verification concepts
- Basic understanding of SystemVerilog and object oriented concepts
- Motivation to learn and discuss questions in the Forums
Description
The Verification industry is adopting SystemVerilog based UVM Methodology at a rapid pace for most of the current ASIC/SOC Designs and is considered as a key skill for any job in the front end VLSI design/verification jobs.
This course teaches
- Basic concepts of two (similar) methodologies - OVM and UVM -
- Coding and building actual testbenches based on UVM from grounds up.
- Plenty of examples along with assignments (all examples uses UVM)
- Quizzes and Discussion forums
- Hands on assignment to build a complete UVM Verification environent for a most popular SOC Bus protocol - APB Bus
Who this course is for:
- Verification engineers who have basic understanding of SystemVerilog but new to OVM/UVM methodology
- Students passing out of VLSI/DigitalDesign/Microelectronics looking for a job in front end of VLSI design
- Any VLSI front end design/verification engineer who wants to increase their job opportunities and skills
Instructor
- 4.3 Instructor Rating
- 11,271 Reviews
- 80,640 Students
- 4 Courses
Experienced and Passionate Verification Engineer with 18+ years of experience in design verification of complex Microprocessors, ASIC and SOC designs at major semiconductor companies like Intel, IBM and other exciting startups.
Co-Author of book "Cracking Digital VLSI Verification Interviews: Interview Success" available on Amazon
Passionate in continuous learning of new and interesting technologies and always ready to share knowledge and help others
Quora Top Writer 2017 ,2018 in VLSI/Semiconductor topics