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2021-01-01 17:43:45
30-Day Money-Back Guarantee
IT & Software Hardware FPGA

Learn FPGA Design With VHDL (Intel/Altera)

Gain a Solid Foundation in VHDL for FPGA Development with Lots of Examples
Rating: 4.2 out of 54.2 (3 ratings)
23 students
Created by Lakshman Athukorala
Last updated 1/2021
English
English [Auto]
30-Day Money-Back Guarantee

What you'll learn

  • We will cover the VHDL language and syntax with lots of example projects
  • Relate VHDL code to hardware implementation
  • Creating FPGA building blocks using VHDL
  • Creating State Machines using VHDL
  • Creating complex FPGA designs from scratch
  • Highlight good design practice & common pitfalls
  • Writing Test Benches in VHDL
  • Simulate & debug FPGA Designs using ModelSim
  • Use the Intel Quartus software to compile and implement projects
  • Use Quartus To Perform Pin Assignments
  • Programming FPGAs using the USB Blaster
  • Using the Quartus Netlist Viewer to view the Hardware Realisation
  • Making sense of the Quartus Fitter Reports
  • Quartus Assignment Editor
  • Quartus Settings, Options & Optimisations
  • Basic Introduction to Quartus Timing Analyser
  • Implement a UART project that communicates over RS232 with a PC
  • Implement a State Machine project
  • Implement a 4 Digit 7-Segment Display to print a Count value
  • Implement a Project to Create A PWM output
  • Implement a Shift Register to Drive LEDs
  • Implement a Project to cover Switch De-bouncing and Synchronisation

Requirements

  • Fundamentals of digital electronics & logic gates
  • Knowledge of binary and hexadecimal number systems

Description

Course Audience :

This course is aimed at students & engineers who want to get into the field of FPGA development using VHDL. No prior knowledge in VHDL/FPGA is assumed so we will start from the very basics.

Students should have a basic knowledge of digital electronics including logic gates and flip-flops.


Course Summary :

This course covers the VHDL language in detail. In between lectures, we will complete a number of fun projects (please see below) with increasing complexity to consolidate the knowledge we have gained during the course. We will go through how to write Test Benches and we will implement a number of Test Benches to verify the UART project. We cover the Intel Quartus software in detail and also go through how to simulate Test Benches using using ModelSim.


Projects (Implemented and Tested On a Cyclone IV Development Board):

1. Reading a switch input and driving an LED output

2. Simple State Machine which reacts to user input and drives a number of LEDs

3. Synchronising and de-bouncing a Switch Input.

4. Generating a PWM output.

5. Designing a Shift Register.

6. 4 Digit 7-Segment display for counting the number of push button activations

7. UART module & State machine for echoing back characters received from a PC over RS232


Intel Quartus Softare:

1. Creating & Compiling a new project

2. Performing pin assignments.

3. Basic introduction to Quartus IP Catalogue.

4. Using the USB Blaster to program the FPGA via JTAG.

5. Using the Quartus Net List Viewer to explore the hardware realisation of your design.

6. Making sense of Quartus Fitter Reports to better understand resource allocation.

7. Using the Quartus Assignment Editor.

8. Overview of Quartus settings, options and optimisations.

9. Basic introduction to timing analyser, timing constraints and SDC files.


Intel ModelSim Starter Edition Software :

1. Creating a new ModelSim Project.

2. Writing & compiling Test Benches.

3. Running simulations.

4. Using the Waveform viewer to analyse results.


Course Details :

We will start by covering the basics of FPGA hardware. This hardware background is vital and as we learn how to write VHDL, we will also refer back to how our code gets implemented in hardware.

In the second section of the course, we will cover the VHDL language in detail. We will cover all the aspects (Signals & Data types, VHDL Keywords & Operators, Concurrent & Sequential statements, Entity & Architecture, Process Block, Generics, Constants & Variables, Records, Component Instantiation, Procedures & Functions, Packages & Libraries and Type Conversions) that are needed to be able to develop complex and advanced FPGA designs. There will be plenty of simple examples to allow you to learn the VHDL language quickly and enable you to confidently write your own code. We will also look at how most of the VHDL language maps to hardware on the actual device.

With this strong foundation in the language, we will look at how to build fundamental FPGA blocks starting from Tri-State Drivers, Registers, Comparators, Multiplexers, Shift Registers, Serialisers, RAMs & ROMs and Finite State Machines. We will look at how to code all of the above structures and also explore how these are implemented in real hardware in the FPGA.

In the next section, we will look at hierarchical design with VHDL. This design practise is used when creating complex designs having more than one design unit. We will explore this concept from an example to see how design units can be joined together to form a hierarchical design.

In the next section we will explore good FPGA design practise. From my experience most beginners in FPGA design make common mistakes and fall into certain traps. Some of these can lead to issues that are very difficult to debug and fix. The idea behind this section is to make you aware of these common pitfalls and explore ways in which we can circumvent these. We will talk about Latches, Generated Clocks, Clock & Data Gating, Benefits of a Register Rich Design, Benefits of Synchronous Design, Dealing With Asynchronous Inputs, Clock Domain Crossing, Designing for Reuse, Signal Initialisation, Synchronising Reset De-assertion, Routing Clocks & Resets and Using PLLs.

By this stage, we would have covered a lot of the theory and also completed a number of design projects so you should have the knowledge to create your own FPGA designs independently. We will now cover design verification. This section will explore how to write test benches. We will explore aspects of VHDL coding styles for writing test benches. We will discuss how to perform file IO for creating input vectors and to store output results. We will also discuss self-checking test benches to help automate the test process.

In the final section of the course, we will design a UART module controlled by a State machine. We will write VHDL code to implement the UART and state machine from scratch. We will use a hierarchical design approach where we will have a number of design units. We will write test benches for each design unit and perform simulations (using ModelSim) for verification.  We will bring all design units together into our top level VHDL module and do a system level simulation. Next, we will explore how to create & configure a project in Intel Quartus to implement our design on our FPGA development board. We will look at how to do the pin assignments and also very briefly look at applying very basic timing constraints to get our design to pass. We will then test the design on real hardware to make sure our design works as intended.



Who this course is for:

  • Graduate students looking for a career as an RTL engineer or Design Engineer
  • Electronics engineers/hobbyists who want to get into the field of FPGA design
  • Those interested in FPGA development who are looking for an introductory course
  • Anyone about to embark on their first VHDL design project

Course content

1 section • 69 lectures • 20h 14m total length

  • Preview11:52
  • Cyclone IV Development Board
    08:18
  • Installing Quartus
    06:47
  • FPGA Fundamentals
    24:50
  • Signals & Data Types I
    31:55
  • Signals & Data Types II
    12:15
  • Constants
    01:50
  • VHDL Operators
    18:53
  • Structure of a VHDL File
    09:31
  • Project : Switch And LED
    25:37
  • The Process Block
    17:51
  • Preview35:15
  • Component Instantiation
    09:27
  • Project : Using Quartus IP Wizard To Generate PLL
    33:49
  • Quartus Netlist Viewer & Fitter Reports
    38:22
  • Quartus Settings & Options
    23:06
  • VHDL Concurrent Statements
    14:15
  • VHDL Sequential Statements
    26:56
  • Signal Assignments I
    14:20
  • Signal Assignments II
    13:08
  • How To Generate A PWM
    09:19
  • Project : PWM LED
    30:41
  • Variables
    06:38
  • Functions and Procedures
    08:10
  • Packages and Libraries
    08:03
  • Parameterised Components
    06:36
  • Type Conversions
    05:59
  • Miscellaneous Topics
    02:22
  • Tri-State Drivers
    01:50
  • Comparators
    03:03
  • Multiplexers
    04:45
  • Shift Registers
    10:57
  • Serialisers
    05:49
  • RAMs & ROMs
    13:17
  • Finite State Machines
    08:28
  • Good Design Practice I
    16:07
  • Good Design Practice II
    08:12
  • Project : LED Shift Register
    36:37
  • How To Debounce A Switch Input
    07:54
  • Project : De-bouncing Asynchronous Input
    11:47
  • Quartus Timing Analyser
    31:57
  • Driving A Seven Segment Display
    12:29
  • Project : 4 Digit Counter Using Seven Segment Display
    59:32
  • Test Benches I
    06:34
  • Test Benches II
    05:16
  • Test Benches III
    04:17
  • UART Block Diagram
    14:22
  • RS232 Protocol
    03:26
  • BaudClkGenerator Block Diagram
    02:26
  • BaudClkGenerator VHDL
    35:33
  • BaudClkGenerator Test Bench
    42:16
  • Serialiser Block Diagram
    01:30
  • Serialiser VHDL
    17:09
  • Serialiser Test Bench
    37:39
  • UART Transmitter VHDL
    22:23
  • UART Transmitter Test Bench
    29:42
  • Shift Register VHDL
    17:25
  • Shift Register Test Bench
    25:41
  • Synchroniser VHDL
    12:52
  • Synchroniser Test Bench
    13:44
  • UART Receiver VHDL
    46:14
  • UART Receiver Test Bench
    39:46
  • Summary So Far
    02:50
  • Top Level Module VHDL
    28:38
  • Top Level Module Test Bench I
    25:37
  • Top Level Module Test Bench II
    35:07
  • Quartus Implementation
    37:16
  • Conclusion
    17:32
  • Quartus Project
    00:03

Instructor

Lakshman Athukorala
Electronics Engineer
Lakshman Athukorala
  • 4.2 Instructor Rating
  • 3 Reviews
  • 23 Students
  • 1 Course

A graduate from the University of Westminster with his Bachelor's degree in Electronics Engineering (1st Class Honours) and a PhD holder in the field of RF and Microwave Filters. He has strong knowledge and experience in Electronic Hardware Design & FPGA development. He has designed complex electronics systems for a wide range of applications including both hardware design, PCB layout, FPGA development and firmware development. He is very passionate about electronics and enjoys  further expanding his knowledge in this field. He enjoys experimenting with development boards, working on new hardware projects, writing FPGA code and generally anything related to electronics.

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