Master FPGA design with VHDL : Sobel Filter Edge Detection

Explore the basics of digital images as a discrete 2d function, compare grayscale and rgb color models, and learn 8-bit per channel representation with practical matlab/octave examples.

Learn how the gradient explains Sobel edge detection by computing partial derivatives, measuring the magnitude, and identifying edge orientation in 1D and 2D images.

Apply convolution by sliding a fixed kernel or mask over an image, multiplying and summing values to produce a filtered image, enabling Sobel edge detection.

Explore how the Sobel filter uses two 3x3 masks to detect vertical and horizontal edges through convolution, producing gradients Jx and Jy.

Apply sobel edge detection by convolving the input image with horizontal and vertical masks to compute gx and gy, approximate magnitude with |gx|+|gy|, threshold to produce a binary edge map.

Learn how to perform sign extension of binary numbers while preserving signedness and value, using zeros for unsigned numbers and ones for signed numbers when expanding from 4-bit to 8-bit.

Demonstrate 1-bit addition and extend to n-bit addition, showing alignment of the lsb and carry in and carry out. Explain unsigned overflow and signed addition using inversion and plus one.

Explore binary addition with practical examples, learning how a carry out differing from a carry in signals overflow, and note the distinction between signed and unsigned overflow.

Explore left and right shifting in hardware design to multiply or divide by powers of two, and use shifts to optimize multiplying a constant 14 with minimal additions.

Explore binary multiplication, where 1×1 corresponds to the and operation, align the lsbs, build partial products with zero placeholders, and sum them for unsigned or signed results with sign extension.

Explains binary division with an example, guiding through 11001 divided by 101, showing bit-by-bit quotient construction, subtraction, and the final remainder.

Explore the numeric_std package in VHDL to perform arithmetic, conversion, and bit manipulation on signed and unsigned numbers, with practical examples of resize, shift, rotate, and two's complement handling.

Presents a finite state machine for the Sobel filter, applying two 3x3 masks, performing 9 multiplications and accumulations per pixel, and estimating edge magnitude by summing absolute values.

Learn a VHDL implementation of the Sobel filter for edge detection, including 3x3 input windows, horizontal and vertical masks, and a finite-state machine to compute magnitude.

Master VHDL signal sizing for Sobel edge detection, from 8 to 21 bits, using sign extension, multiplication, and carefully planned accumulation to prevent overflow.

Simulate the Sobel filter architecture and visualize the 3x3 horizontal and vertical kernels with ready/valid data flow, throughput, and magnitude calculation for edge detection.

Explore the architecture of a Sobel filter edge detector, with grayscale image storage, a 3x3 window, a memory FSM, and on-board VGA display of original and edge images.

Configure three memories for Sobel edge detector: an image ROM for original image, a color palette ROM to 8-bit colors generated by Python, and an image ROM for filtered output.

Implement a VHDL edge detector with a Sobel filter using an automatically generated image ROM for variable width and pixel depth, feeding a 3x3 window to the solver filter.

Learn a VHDL implementation of a 3x3 Sobel edge detector, featuring a finite state machine, ROM storage, thresholding, and VGA display of the raw and filtered images.

Focus on image processing with the sobel filter, while noting VGA is out of scope; the VGA interface uses red, green, blue and h-sync and v-sync to position pixels.

Organize the fpga project with a root Makefile that automates simulation, vhdl generation, and Sobel filter output images, while using Python to build ROMs and manage memory-efficient input formats.

Automate Sobel edge-detection with a configurable Makefile and Python tools that generate the image ROM, color palette ROM, and edge detection package, run simulations, and convert memory dumps to images.

Demonstrates on-board tests and simulations of the Sobel filter for edge detection, showing original and filtered images from ROM, threshold-based binarization, and how image size and memory limits affect results.

Celebrate completing the course on FPGA design with VHDL and image processing, including Sobel filter edge detection, and look forward to more RISC-V CPU courses.