Learn FPGA Design with VHDL: Digital Logic & Simulation

Explore number systems and binary arithmetic, where bits form numbers and column weights map to decimal values. Compare hex representation and signed binary forms, including sign magnitude and two's complement.

Explore combinational logic blocks without memory, described by truth tables and built from basic gates—not, and, or, xor, nand, and nor—linking algebraic functions to digital logic design.

Explore logic circuit design and minimization with canonical forms—the sum of minterms and the product of sums—and simplify Boolean equations using kernel maps with a,b,c inputs.

Explore combinational logic circuits, including multiplexers, decoders, and encoders, and analyze half and full adders, ripple carry adders, and carry look-ahead architectures.

Explore sequential logic circuits and flip flops, including s-r, d, j-k, and t types, clock edges, and reset behavior. Examine registers and shift registers, plus ram and rom memory.

Examine timing and hazards in digital circuits, covering propagation and contamination delays, setup and hold times, and clock skew. Use clock trees, buffers, and equal path delays to prevent glitches.

Explain that a finite state machine is a discrete-time system that uses inputs to determine next state and produce outputs, with the state and input uniquely defining the next state.

Use finite state machines to formalize the relation between circuit inputs and outputs, enabling functional specification, modeling system as a single state machine, and supporting verification, simulation testing, and synthesis.

Explore finite state machines, comparing Mealy and Moore models, and the Medvedev subclass, focusing on how outputs depend on inputs and state versus state alone.

Describe finite state machines with state tables and graphs, showing next state from present state and input, and output from present state, for five states S0–S4 encoded in three bits.

Explore how the bits encode each FSM state and how different encodings impact hardware behavior and speed, while focusing on the FSM's overall behavior.

Define the finite state machine states, draw the state diagram, and implement three concurrent VHDL processes: present state (clocked) process, output process, and next state (combinatorial) process.

Outlines a traffic light finite state machine with green, yellow, and red. Shows a VHDL implementation using clock and sensor to drive red, green, and yellow outputs.

Design an FPGA vending machine controller in VHDL using ten-state FSM to accept nickel, dime, or quarter for 0.25 and dispense candy with candy out, nickel out, and dime out.

Explore how configurable logic blocks form the core of FPGAs, combining lookup tables, flip-flops, multiplexers, and fast arithmetic logic within a programmable routing matrix.

Explore programmable routing in FPGAs, including connection boxes, CBS, and switch matrices, and examine clock trees, buffers, and routing delays that affect clock skew and the critical path.

Describe input/output blocks at the FPGA and distinguish CMOS, TTL from differential LVDS, emphasizing noise immunity. Outline configuring a gp io with constraints, voltage, standard selection, synthesis, and testing.

Learn how FPGA DSP blocks enable high-performance multiply-accumulate operations, with a DSP 48 e1 diagram and an arithmetical logical unit, and arithmetic units built from lookup tables and flip-flops.

Explain fpga memory architecture, covering block ram, distributed ram, fifo, and dual-port options, including true dual-port ram, external memory types sram, sdram, flash, and axi interfaces.

Define clocking concepts in FPGAs, including clocks, jitter, and clock domains. Explain how PLLs, MCMs, and clock buffers manage frequency, phase, and skew.

Explain the basic structure of a VHDL file, including library and package declarations, the entity with inputs and outputs, and the architecture body for a simple end gate.

Identify three key VHDL elements: signals, a process, and concurrent statements. Signals are internal wires; a process runs in parallel with sequential statements.

Explore combinational circuits in VHDL, where outputs depend only on current inputs, with no memory or feedback. Build a 2-to-1 multiplexer and a half adder, illustrating xor, sum, and carry.

Explore how to simulate VHDL code and verify its behavior before synthesis, using testbenches, waveforms, and industry tools like Modelsim, Questa, Vivado simulator, and open source options.

Learn to install ghdl, a free vhdl simulator, and gtkwave, a free waveform viewer on Ubuntu, with step-by-step commands to update the system and install each tool.

Explore the source files for the end gate simulation, including the gate entity and architecture, and a testbench that applies A and B inputs and observes y.

Analyze the end gate VHDL design and testbench for semantics and syntax, elaborate the testbench, then run the simulation and view the waveform with GTK wave.

Learn to simulate an and gate design in VHDL by analyzing the testbench, elaborating the design, and running a 15 ns simulation with a VCD waveform view in GTKWave.

Explore building a two-bit adder in VHDL, generate test vectors with Python, and verify with a testbench that reads stimulus and expected vectors to confirm sum and carry.

Run the golden model to generate inputs, analyze the testbench and design, simulate, and dump waveforms to a VCD file to verify the two-bit adder's sum and carry.

Explore the I2C protocol that connects devices using two wires, SDA and SCL. Master-slave roles, seven- or ten-bit addressing, and the start, stop, and acknowledge sequence drive data transfer.

Explore the SPI protocol, a four-wire full-duplex master-slave bus with Mosi, miso, serial clock, and slave select, covering no addressing, speeds from 1 to 50 MHz, and mode compatibility.

Explore the uart protocol, an asynchronous two-wire communication using tx and rx, timed to a common baud rate with start, data (lsb first), and stop bits.

Explore the acsi protocol inside FPGAs and chips, detailing AXI4, AXI4-Lite, and AXI4-Stream as a five-channel internal bus with two read and three write channels for memory and registers.

Explore the ethernet protocol and its seven osi layers, focusing on the physical and data link layers, mac addressing, crc, and how ethernet frames are constructed and checked.

Explore the PCI Express protocol, a high-speed serial interconnect between root complex and endpoint, using lanes, differential signaling, and a three-layer architecture.

Explore the HDMI communication protocol for transmitting uncompressed digital video and audio from a source to a display, including TMDS encoding and differential signaling for red, green, and blue data.

Explore how the can bus enables multi-master serial communication across automotive and industrial systems. Implement the can controller and transceiver in FPGA designs to manage frame creation, arbitration, and CRC.

Conclude the course with a final bonus lecture that celebrates finishing the class and offers 1-to-1 teaching sessions for personalized guidance, live troubleshooting, and real-world Q&A.