Master FPGA design with VHDL : Tic-Tac-Toe game with VGA

visualize the tic tac toe architecture with a 100 mhz clock divided to 25 mhz for the vga drawing system, rendering the grid, crosses, and circles via a navigation fsm.

Explore the top level of a tic tac toe FPGA design in VHDL, detailing the entity, inputs and outputs, debounce of five buttons, and a VGA controller setup.

Learn to implement a debounce button in VHDL that eliminates contact bounce and produces a single one-cycle pulse by slow clocking, input registration, and edge detection, with a testbench demonstration.

Generate a 25 MHz VGA clock from a 100 MHz input with a synchronous two-bit clock divider. The MSB of the counter yields the 25 MHz signal.

Explore the VGA analog video interface, 640x480 output, RGB color from 3 red, 3 green, 2 blue bits, and hsync and vsync timing with front and back porches.

Implement a 640x480 VGA controller at 60 Hz using two counters for horizontal and vertical timing, accounting for front/back porches and hsync/vsync, with a display enable signal driving RGB values.

Implement a vga controller in vhdl for a 640x480 display with 800 by 525 timing. Generate hsync, vsync, and display enable while counting horizontal and vertical indices.

Observe a VGA controller in simulation using a simple testbench and 25 mhz pixel clock; verify hsync, vsync, and display enable with 640x480 in 800x525 timing.

Explore the navigation finite state machine for the tic-tac-toe grid, detailing how next, previous, and start inputs move through the nine cell states and wrap around from 2,2 to 0,0.

The lecture explains the game FSM that controls tic-tac-toe with push buttons and a 100 MHz clock, mapping states to cells, navigating, validating moves, and factorizing logic for readability.

Draws a 3×3 tic-tac-toe grid on VGA by updating RGB signals with a 25 MHz clock, starting white and drawing yellow grid lines, cross, circle, and green position square.

Iterate the nine cells with a for loop to draw the grid and compute each cell's top-left. In the current cell, render a green square with 3-pixel thickness on VGA.

Draws a green three-pixel-thick square border on the VGA screen, highlighting the current cell, and updates with a blue circle or red cross after validation.

Explore drawing on screen by using center coordinates and circle equations to render borders and crosses for each tic-tac-toe cell on a VGA display.

Learn to map tic-tac-toe top level ports to FPGA pins using a constraint file, including 100MHz clock, reset, five push buttons, and VGA outputs, with editor-based or tool-based approaches.

Create a project in ISE14.7, select the correct board values, add VHDL sources and constraints, generate the bitstream, and program the FPGA via the manufacturer software.

Demonstrates a tic-tac-toe game designed in VHDL for FPGA with VGA, including reset, idle state, start, cell navigation, and occupancy rules validated by the FSM.

Celebrate completing the course and reflect on design and implementation. Share feedback for future topics and stay tuned for more projects.