Master FPGA design with VHDL : Image transfer with UART

Study UART, a two-wire asynchronous serial protocol with frames carrying start, data, optional parity, and stop bits. Transmitter serializes parallel data; receiver deserializes it by sampling at the baud rate.

Explore uart parity theory: the transmitter calculates a parity bit (even or odd) from the data, and the receiver recomputes it to detect single-bit errors.

Explore a UART data transmission example in VHDL. It shows sending 8 data bits with an optional parity bit using a shifting buffer, start/stop bits, and baud pulses.

Describe UART data reception in a VHDL design using oversampling to sample at the bit middle, receive LSB first with optional parity, and verify stop and parity for errors.

Illustrates a UART block diagram for hardware implementation, with baud rate and oversampling counters and 16x sampling, and reception/transmission FSMs handling RX/TX shift registers, start/stop/parity framing.

Explore uart implementation in vhdl, focusing on input/output ports and core parameters: 100 mhz clock, 19200 baud, oversampling 16, 8 data bits, optional parity, with tx/rx signals and serialized tx pin.

Study the uart clock divider in a fpga, generating baud and oversampling pulses from a 100 mhz clock and using counters for 19200 baud with 16x oversampling.

Demonstrates a UART receiver in VHDL that uses rxCount and oversampling osCount to sample bits in the middle, shift data into rx buffer, and perform stop and parity checks.

Master FPGA design with VHDL demonstrates a UART transmitter that sends an 8-bit data frame with start/stop bits and optional parity, using a TX buffer and parity calculation.

Instantiate a uart top level configured for 100 mhz, 19200 baud, 16x oversampling, 8 data bits, even parity; it receives a byte, inverts it, and sends it back.

Simulate the uart in a test bench with 100 mhz clock, 19200 baud, 1640 oversampling, 8 data bits and even parity; transmit a pattern and receive in full duplex.

Examine how a 100 mhz clock drives uart reception at 19200 baud, using 16x oversampling to sample the rx in the middle and build the data with parity checks.

Serialize data for uart transmission from fpga by shifting lsb first each baud pulse, using a buffer with data and start, parity, and stop bits, moving from idle to busy.

Send an image from the computer side over UART with a Python script, resizing 1024x1024 to 256x256 and quantizing to 3 red, 3 green, 2 blue bits before byte transfer.

Understand a Python script that sends and receives a 256x256 8-bit image over UART for FPGA transfer, quantizing to 3-3-2 bits and producing binary and PNG outputs.

Map the UART top-level ports to board pins using a constraints file, either auto-generated or manufacturer-provided, then synthesize the design and generate the bitstream to test the system.

Explore the synthesis flow in FPGA design using the iSEE interface: create a project, add files and the constraint file, synthesize, implement, and generate the bitstream to configure the FPGA.

Demonstrates image transfer over uart with an fpga by loading a bitstream, configuring serial communication at 19200 baud, and exchanging a pixelated image using a Python script.

Review the UART protocol theory and its hardware implementation in VHDL. Outline a system for image transfer between a computer and an FPGA via UART.