Master FPGA design with VHDL : Alarm Clock

Name: Master FPGA design with VHDL : Alarm Clock
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Design and Build a Functional Alarm Clock Using FPGA and VHDL: From Concept to Hardware Implementation

Created byAnas F.

Last updated 10/2025

English

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What you'll learn

Specification Analysis: Understanding system requirements and design specifications for an FPGA-based project.
Digital Logic Design with VHDL: Designing combinational and sequential logic circuits.
FPGA Basics: Gaining hands-on experience with FPGA hardware, toolchains, and development workflows.
Buzzer device: Learning how to interface and drive a buzzer for ring tone generation.
7-Segment Display: Learning how to interface and drive an external 7-segment display for time visualization.
Push Button and Switch Interfacing: Understanding how to connect and debounce input devices like buttons and switches.
FPGA Synthesis and Simulation: Using simulation tools to verify the design before synthesizing it onto hardware.
Demonstrating the Final System: Presenting a working alarm clock system running on an FPGA board.

Course content

5 sections • 20 lectures • 2h 12m total length

Introduction1:38
Explore FPGA design with VHDL by building an alarm clock, covering processes, counters, multiplexers, combinational and sequential circuits. Interface a four-digit seven-segment display and buzzer, simulate, and test on board.
Specification7:24
Design alarm clock on FPGA with VHDL by defining objective and requirements and translating them into a technical specification for set clock, set alarm, buzzer, and four-digit seven-segment display modes.

Material used4:33
The lecture lists tools and hardware for the fpga alarm clock, including iac 14.7 for synthesis, modelsim for simulation, and v2 fpga board with a four-digit seven-segment display and buzzer.
Mimas V2 FPGA board3:36
Wire a Spartan-6 FPGA board for a simple alarm clock using three switches, a reset button, and a four-digit seven-segment display with a buzzer, detailing the pin usage and connections.
Buzzer4:07
Drive a buzzer with an FPGA using PWM to generate tones. The demonstration uses a 1-second period, 0.5 seconds on/off, and a 20 ms tone to mimic an alarm clock.
4 digits 7 segments display12:12
Explore the four digit seven segment display and its multiplexed control using an external peripheral, highlighting common cathode configuration, selector pins, and lighting segments A to J and the dot.
Breadboard4:45
connect a four-digit seven-segment display to an fpga via a breadboard to prototype without soldering, using i/o pins and a constraints file to map signals.

Input/Output ports2:38
Analyze the input/output ports of the alarm clock design, focusing on clock and negative reset, set time/alarm signals, push-button inputs, and seven-segment, digit selector, buzzer outputs.
Debounce button6:01
Implement debounced button input by registering the input multiple times with a slow clock to produce a single-cycle pulse, removing bounce and metastability so increments and decrements respond reliably.
Clock divider11:01
Learn how a 100 MHz clock feeds a clock divider that generates one second, 500 ms, and 10 ms pulses using five 32-bit counters for buzzer, display, and demonstration.
Counters12:03
Examine how a single sequential process drives the current time counters (seconds, minutes, hours). Include the alarm counter, debounced push buttons, and wrap-around for hours and minutes.
Binary to BCD11:45
Convert binary to bcd to display decimal digits on digital clocks and calculators, using a six-bit input and two four-bit digits per hour and minute via a shift-and-add-three double-dabble approach.
Buzzer controller8:27
Explains the buzzer controller at the alarm clock top level, triggering a 10-second buzzer when the current time matches the alarm time, using buzzer state, pulse enable, and pulse tone.
Display controller8:45
Control a four-digit seven-segment display with a multiplexed eight-segment bus and four-bit selector, cycling digits 0–3 using a bcd to seven-seg decoder, with 2.5 ms timing.
Alarm clock3:12
Design an alarm clock in VHDL by wiring a clock divider, debounce modules, binary-to-bcd converters, and a seven-segment display, enabling current or alarm time display, increment/decrement functionality, and buzzer control.

Simulation15:01
Build and run a VHDL testbench to visualize alarm clock signals in simulation, including clock, reset, debounce, and current time versus alarm time displayed via binary-to-bcd seven-segment outputs.
Constraints file8:58
Synthesize the alarm clock design for the FPGA, place gates, and route connections. Map inputs and outputs to physical pins using a manufacturer reference constraint file.
Synthesis1:28
Create and configure an FPGA project in ISC Project Navigator, selecting the correct target device and constraint file. Generate the bitstream and program the FPGA, noting a preference for Vivado.
Demonstration4:06
Demonstrates an FPGA-based alarm clock in VHDL, showing time counting, display, alarm activation, and internal time keeps counting while configuring alarms with switches.

Requirements

Basic notions on digital electronics and VHDL are needed to get the most from this course

Description

This course is designed to immerse you in the world of hardware engineering. The course will guide you through the process of converting requirements and needs into practical and efficient designs. You will explore the basic concepts of digital circuits and VHDL coding rules and syntax. Furthermore, the course will cover the use of constraints files, synthesis and simulation of HDL designs, enabling you to verify the correctness of your circuits before physical implementation. By the end of the course, you will have a comprehensive skill set to design, implement, and test digital systems.

To achieve all of the above, we will design in VHDL an Alarm Clock on FPGA. One external 4 digits 7-segments display will be connected to the FPGA via wires to display the time in HH:MM format. This is ideal to learn about FPGA PMODs and IO pins. The design will allow the user thanks to switches to set either the current time or the alarm. In "SET" mode, the configuration of the clock and alarm will be done by pressing push buttons to either increment minutes or hours. When the current time reaches the configured alarm set by user, a buzzer connected to FPGA will buzz for one minute.

By the end of the course, students will have the practical skills and experience required to design, implement, and verify their own fully functional digital alarm clock system on an FPGA, providing a solid foundation for further FPGA and digital design projects.

Who this course is for:

Beginner Digital Electronics students or anyone interested in learning FPGA design

Master FPGA design with VHDL : Alarm Clock

What you'll learn

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Course content

Introduction2 lectures • 9min

Understanding the material5 lectures • 29min

VHDL implementation8 lectures • 1hr 4min

Testing on FPGA4 lectures • 30min

Conclusion1 lecture • 1min

Requirements

Description

Who this course is for: