JTAG: Boundary Scan, JTAG standard, TAP and DFT Introduction

Explore JTAG signals and key terms, including debugger, target, tap controller, and test access port, and explain signals such as TDI, TDO, TMS, TC, reset, and reference voltage.

Explain how Jtag registers form a serial daisy chain, with the instruction register selecting the active data register, and status, address, ID code, bypass, and command registers guiding read/write transactions.

Ijtag extends the Jtag standard to access and control on-chip instruments such as BIST, DAC, and ADC in a SoC, boosting testability with ATP patterns for simulation, FPGA, or silicon.

Learn to access a second tap in a two-tap JTAG chain by bypassing the first tap via its bypass register, selecting the ID code register, and shifting to read ID.

Synchronize the jtag clock with the cpu clock using a clock synchronization module to enable boundary scan read/write via the jtag port, maintaining a 1:8 ratio to prevent jtag failure.

Showcases host interface that connects a test pc to the soc’s jtag port via a two-wire tc and tms link, converting to four jtag signals for debug and memory read/write.

Explore software debuggers for jtag, including MDB by Synopsys and T32 by Lauterbach, that graphically display registers, memory, and call stack, enable firmware loading, run/stop control, and register editing.

Explore DFT techniques to add built in testability, including ad hoc DFT in crucial domains, built in self test, test pattern generator, and boundary scan with JTAG for serial test.