JTAG: Boundary Scan, JTAG standard, TAP and DFT Introduction

Explore the JTAG standard in depth, including input, output, and clock signals, the data, instruction, and bypass registers, and the TAP controller with its state diagram.

Explore JTAG signals and key terms, including debugger, target, tap controller, and test access port, and explain signals such as TDI, TDO, TMS, TC, reset, and reference voltage.

Explain how Jtag registers form a serial daisy chain, with the instruction register selecting the active data register, and status, address, ID code, bypass, and command registers guiding read/write transactions.

Drive boundary scan with the tap controller, the test access port linking device-specific logic to the jtag standard, guided by tms and tck in a 16-state machine.

The tap state machine governs the jtag boundary scan with 16 states, starting from the power-on test logic reset, using tms and tc clock to capture, shift, and update registers.

Track how the TAP controller state machine transitions with the TMS signal, handling reset, select instruction and data registers, and perform capture, shift, and update operations to transfer data.

Explore how the tap controller operates via its state machine, driven by tc and tms, selecting instruction or data registers through a demux, and shifting values into the registers.

Explain how the tap shift operation routes TDI through the instruction register to select bypass, ID code, and boundary scan data registers, with lengths varying by instruction.

Identify the ID code register as the default data register in the JTAG data path, selected by instruction 1100, with version, part number, and manufacturing ID stored there.

Read the 32-bit idcode from the JTAG data register using a Trace32 Lauterbach debugger, guiding the tap through capture-dr, shift-dr, and update-dr to output the value.

Explore how boundary scan cells form boundary scan register and a serial scan chain accessed via TDI and TDO through the TAP controller, enabling data capture and observation during testing.

Understand how JTAG boundary scan cells form a serial boundary scan register, with bypass, ID code, sample, preload, and X test instructions controlling data flow, clamps, and high impedance states.

Enable the JTAG debug interface and explore JTAG standard types, including compact JTAG and multicore connections, daisy chaining cores, clock domain synchronization, and enabling the host interface for debugging.

Compare JTAG and cJTAG: JTAG uses four external signals (TC, TMS, TDR, TDVO) while cJTAG uses two (TC, TMC) with an adaptor converting to four, reducing wiring and bandwidth.

Ijtag extends the Jtag standard to access and control on-chip instruments such as BIST, DAC, and ADC in a SoC, boosting testability with ATP patterns for simulation, FPGA, or silicon.

Examine multicore JTAG connections and topologies, including serial, star, and two-wire configurations, with common TC, TMS, and reset pins, and learn bypass and module selection for targeted debugging.

Learn to access a second tap in a two-tap JTAG chain by bypassing the first tap via its bypass register, selecting the ID code register, and shifting to read ID.

demonstrates configuring three jtag taps in a serial multicore topology, selecting bypass registers and data registers through the instruction register path and shift operations.

Synchronize the jtag clock with the cpu clock using a clock synchronization module to enable boundary scan read/write via the jtag port, maintaining a 1:8 ratio to prevent jtag failure.

Showcases host interface that connects a test pc to the soc’s jtag port via a two-wire tc and tms link, converting to four jtag signals for debug and memory read/write.

Explore JTAG debuggers and hardware forming the physical host-to-SoC connection, review debugger software tools, and examine design for testability with boundary scan cells for post-manufacture debugging.

Explore hardware JTAG debuggers, including six-pin Digilent and twenty-pin Ashling or Lauterbach with a converter; install the driver and transmit data via USB or Ethernet to produce JTAG signals.

Explore software debuggers for jtag, including MDB by Synopsys and T32 by Lauterbach, that graphically display registers, memory, and call stack, enable firmware loading, run/stop control, and register editing.

Learn how JTAG, the joint test action group, enables debugging via boundary scan and firmware loading, and how the TAP controller coordinates instruction and data registers.

Apply design for testability (DFT) concepts to improve testing efficiency in VLSI, focusing on controllability and observability to reduce test cost, timing, and enhance product quality.

Explore DFT techniques to add built in testability, including ad hoc DFT in crucial domains, built in self test, test pattern generator, and boundary scan with JTAG for serial test.

Describe boundary scan characteristics using the boundary scan description language (BSDL), a VHDL subset for JTAG, detailing instruction register length, opcodes, and ID code and data registers and port mapping.

Explore boundary scan testing and the JTAG standard, including JTAG signals and registers, various JTAG types and connections, and the range of hardware debuggers and tools for host machines.