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Verilog HDL : Fully Hands on Learning Experience
Rating: 4.0 out of 5(13 ratings)
1,007 students

Verilog HDL : Fully Hands on Learning Experience

Verilog : Hardware Description Language
Created byAK APT LOGICS
Last updated 4/2026
English

What you'll learn

  • Verilog Syntax and Comments
  • Verilog White Spaces
  • Verilog Operators
  • Verilog Number Format
  • Verilog Sized Numbers
  • Verilog Sized Numbers Examples
  • Verilog Unsized Numbers
  • Verilog Negative Numbers
  • Verilog Strings
  • Verilog Keywords
  • Verilog Identifiers

Course content

2 sections • 38 lectures • 16h 42m total length

  • A Small Request From Myside0:38
  • Verilog HDL Part 1 Introduction to Verilog HDL #VLSI #Verilog #design #verificat46:57
  • Verilog HDL Part 2 | Introduction to Verilog | Verilog | VLSI | AK APT LOGICS #v1:08:51

    Explore Verilog as a hardware description language and learn how to write synthesizable design code and testbench code to verify functionality with test vectors and simulations.

  • ASIC Design Flow Explained | What is VLSI & ASIC? | Verilog HDL Part 3 | AK APT1:20:56
  • Verilog HDL Tutorial Part 4 | Verilog Syntax & Comments Explained | Verilog Prog13:28
  • Verilog HDL Tutorial Part 5 | Verilog White Spaces in Syntax | Verilog Programmi8:22
  • Verilog HDL Tutorial Part 6 | Operators in Verilog | Unary, Binary & Ternary Ope10:24

    Explore unary, binary, and ternary operators in Verilog HDL, classified by operand count, with examples like negation, minus, bitwise or, and the conditional operator using the ?: form.

  • Verilog HDL Tutorial Part 7 | Number Formats in Verilog | Decimal, Binary, Octal3:45
  • Verilog HDL Tutorial Part 8 | Sized Numbers in Verilog | Binary, Decimal, Hexade23:23

    Learn to express Verilog size numbers as decimal width with a base and digits, such as 3'b010 or 3'd2, using d, b, h, or o.

  • Verilog HDL Tutorial Part 9 | Sized Examples | Errors, Warnings, Rectification,32:18
  • Verilog HDL Tutorial Part 10 | Unsized Numbers in Verilog | Default Decimal & Bi14:06
  • Verilog HDL Tutorial Part 11 | Negative Numbers in Verilog | Signed vs Unsigned,26:07
  • Verilog HDL Tutorial Part 12 | Strings in Verilog | ASCII, Storage, and Display39:02
  • Verilog HDL Tutorial Part 13 | Identifiers in Verilog | Naming Rules and Example3:36

    Learn how Verilog identifiers name variables, including allowed characters (letters, digits, underscores, and the dollar sign), case sensitivity, and the rules for valid names with examples.

  • Verilog HDL Tutorial Part 14 | Keywords in Verilog | Reserved Words Explained2:34

    Keywords are reserved Verilog identifiers with predefined meanings for language constructs, and the lecture lists important keywords like begin, case, default, module, and initial.

  • Verilog HDL Tutorial Part 15 | Verilog Data Types Explained | Value Set (0,1,x,z5:53
  • Verilog HDL Tutorial Part 16 | Nets and Variables in Verilog | Wire Explained wi32:05

    Master Verilog data types by examining nets and variables. Understand wires as transmission elements, scalar and vector forms, input/output labeling, and internal wires.

  • Verilog HDL Tutorial Part 17 | Variables in Verilog | reg Data Type Explained |32:40
  • Verilog HDL Tutorial Part 18 | Integer Data Type in Verilog | Signed vs Unsigned19:57
  • Verilog HDL Tutorial Part 19 | Time and Realtime Data Types in Verilog | 64-bit29:29
  • Verilog HDL Tutorial Part 20 | Real Data Type in Verilog | Floating Point Precis23:44
  • Verilog HDL Tutorial Part 21 | Strings in Verilog | reg Storage & ASCII Explaine24:38

    Learn how Verilog stores strings with reg storage and ASCII, using vector ranges to hold multiple characters and eight bits per character, and how width causes truncation or zero padding.

  • Verilog HDL Scalars and Vectors47:00

Requirements

  • VS code or any eda playground usage should be known to start the course

Description

This course is designed for beginners eager to learn Verilog HDL for digital and VLSI design. The first five videos provide a comprehensive introduction, starting with the basics of hardware description languages and moving towards practical Verilog coding principles.

  1. Introduction to Verilog HDL: Covers the fundamentals of what Verilog is, its history, applications in digital system design, design vs. verification, comparisons with VHDL and software languages, and the levels of abstraction in hardware design.

  2. Basic Syntax and Data Types: Introduces the syntax of Verilog, key data types such as wire and reg, and how hardware constructs like gates and flip-flops map to Verilog structures.

  3. Operators and Expressions: Explains the use of arithmetic, logical, and bitwise operators in Verilog coding along with examples to build simple combinational logic.

  4. Module and Hierarchy Concepts: Details the structure of Verilog modules, port declarations, and how to instantiate modules to build hierarchical designs.

  5. Behavioral Modeling and Conditional Statements: Explores behavioral modeling using always blocks, if-else conditions, case statements, and describes how to model sequential logic.

This course equips learners with foundational skills for Verilog programming, focusing on clarity, reusability, and practical digital system design concepts. It is ideal for students preparing for GATE or starting careers in VLSI design and verification.


Who this course is for:

  • Beginner who eagarly wanted to start the Verilog HDL with fully hands on Experience

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