Verilog HDL : Fully Hands on Learning Experience

Name: Verilog HDL : Fully Hands on Learning Experience
Rating: 4.0 (13 reviews)

Verilog : Hardware Description Language

Created byAK APT LOGICS

Last updated 4/2026

English

What you'll learn

Verilog Syntax and Comments
Verilog White Spaces
Verilog Operators
Verilog Number Format
Verilog Sized Numbers
Verilog Sized Numbers Examples
Verilog Unsized Numbers
Verilog Negative Numbers
Verilog Strings
Verilog Keywords
Verilog Identifiers

Course content

2 sections • 38 lectures • 16h 42m total length

A Small Request From Myside0:38
Verilog HDL Part 1 Introduction to Verilog HDL #VLSI #Verilog #design #verificat46:57
Explore verilog hdl as a hardware description language for designing and verifying digital circuits in vlsi, covering behavioral modeling, synthesis, and test cases.
Verilog HDL Part 2 | Introduction to Verilog | Verilog | VLSI | AK APT LOGICS #v1:08:51
Explore Verilog as a hardware description language and learn how to write synthesizable design code and testbench code to verify functionality with test vectors and simulations.
ASIC Design Flow Explained | What is VLSI & ASIC? | Verilog HDL Part 3 | AK APT1:20:56
Explore the ASIC design flow from requirements and architecture to RTL, verification, and fabrication, including VLSI, Verilog HDL, RTL vs behavioral, synthesis, and post-silicon validation.
Verilog HDL Tutorial Part 4 | Verilog Syntax & Comments Explained | Verilog Prog13:28
Master Verilog syntax with practical demonstrations of lexical conventions, semicolon termination, and case sensitivity. Learn about comments—single-line and multiline—and their nesting rules, reflecting Verilog's C-like heritage.
Verilog HDL Tutorial Part 5 | Verilog White Spaces in Syntax | Verilog Programmi8:22
Learn how Verilog handles white spaces in syntax, including spaces, tabs, and newlines for readability, and note that strings count spaces while code ignores leading whitespace.
Verilog HDL Tutorial Part 6 | Operators in Verilog | Unary, Binary & Ternary Ope10:24
Explore unary, binary, and ternary operators in Verilog HDL, classified by operand count, with examples like negation, minus, bitwise or, and the conditional operator using the ?: form.
Verilog HDL Tutorial Part 7 | Number Formats in Verilog | Decimal, Binary, Octal3:45
Explore Verilog number formats, including decimal, binary, octal, and hexadecimal, noting that simulators treat numbers as decimals by default and using prefixes to specify other radix bases.
Verilog HDL Tutorial Part 8 | Sized Numbers in Verilog | Binary, Decimal, Hexade23:23
Learn to express Verilog size numbers as decimal width with a base and digits, such as 3'b010 or 3'd2, using d, b, h, or o.
Verilog HDL Tutorial Part 9 | Sized Examples | Errors, Warnings, Rectification,32:18
Explore sized formats in Verilog HDL through hands-on examples of decimal, binary, octal, and hexadecimal representations, and learn how C-style literals translate in Verilog, including common errors, warnings, and rectifications.
Verilog HDL Tutorial Part 10 | Unsized Numbers in Verilog | Default Decimal & Bi14:06
Explore unsized numbers in Verilog HDL, including default decimal interpretation, base format specifications, and how default versus actual bit sizes are determined, with examples using integer, hex, and display formatting.
Verilog HDL Tutorial Part 11 | Negative Numbers in Verilog | Signed vs Unsigned,26:07
Learn how Verilog represents negative numbers using two's complement, contrasts signed and unsigned types, and uses six-bit vectors with the minus sign placed before the size in the literal.
Verilog HDL Tutorial Part 12 | Strings in Verilog | ASCII, Storage, and Display39:02
Learn how Verilog stores strings as ASCII characters, one byte per character, using reg and arrays, and print strings or characters with $display and format specifiers.
Verilog HDL Tutorial Part 13 | Identifiers in Verilog | Naming Rules and Example3:36
Learn how Verilog identifiers name variables, including allowed characters (letters, digits, underscores, and the dollar sign), case sensitivity, and the rules for valid names with examples.
Verilog HDL Tutorial Part 14 | Keywords in Verilog | Reserved Words Explained2:34
Keywords are reserved Verilog identifiers with predefined meanings for language constructs, and the lecture lists important keywords like begin, case, default, module, and initial.
Verilog HDL Tutorial Part 15 | Verilog Data Types Explained | Value Set (0,1,x,z5:53
Explore Verilog HDL data types, including storage and transmission elements, and learn the four primary values 0, 1, x, z, plus the meaning of high impedance in hardware modeling.
Verilog HDL Tutorial Part 16 | Nets and Variables in Verilog | Wire Explained wi32:05
Master Verilog data types by examining nets and variables. Understand wires as transmission elements, scalar and vector forms, input/output labeling, and internal wires.
Verilog HDL Tutorial Part 17 | Variables in Verilog | reg Data Type Explained |32:40
Explore Verilog HDL variables and the reg data type, contrast nets and storage elements, and master scalar and vector representations, part and bit select, and signedness in always blocks.
Verilog HDL Tutorial Part 18 | Integer Data Type in Verilog | Signed vs Unsigned19:57
Explore the Verilog integer data type: its 32-bit default size, default value x, how integer differs from int in SystemVerilog, and that it is signed by default.
Verilog HDL Tutorial Part 19 | Time and Realtime Data Types in Verilog | 64-bit29:29
Explore Verilog HDL time data types, including time (unsigned 64-bit) and real time (floating point, signed), with format specifiers and default value behavior.
Verilog HDL Tutorial Part 20 | Real Data Type in Verilog | Floating Point Precis23:44
Learn how to declare and use the real data type in Verilog to store floating point values, control precision, and observe its default signed, 64-bit behavior.
Verilog HDL Tutorial Part 21 | Strings in Verilog | reg Storage & ASCII Explaine24:38
Learn how Verilog stores strings with reg storage and ASCII, using vector ranges to hold multiple characters and eight bits per character, and how width causes truncation or zero padding.
Verilog HDL Scalars and Vectors47:00
Engage in a hands-on learning experience with Verilog HDL scalars and vectors, mastering data types, bit widths, and practical hardware design applications.

Design and Verification of Not gate in gate level Modelling25:46
Design and verify a not gate using gate level model in Verilog, with hands-on coding in EDA Playground, including a testbench and gate level primitives.
Design and Verification of Not gate in Data Flow Modelling7:33
Design a not gate using RTL and dataflow models in Verilog, and verify its behavior with a test bench, waveform, and console output.
Design and Verification of Not gate in Behavioural Modelling23:15
Explore the design and verification of a not gate in Verilog HDL using the behavioral modeling approach, focusing on always blocks, test benches, and differences from dataflow and structural styles.
Design and Verification of Not gate in Switch Level Modelling38:37
Design and Verification of Nand Gate in Gate Level Modelling20:14
Design and Verification of Nand Gate in Dataflow Modelling29:49
Design and Verification of Nand Gate in Behavioural Modelling34:10
Design and Verification of Nand Gate in Switch Level Modelling46:01
Design and Verification of AND Gate in Gate Level Modelling28:33
Design and Verification of AND Gate in Dataflow Level Modelling14:58
Implement the and gate in dataflow modeling with the assign keyword and y equals a and b, and verify via the test bench. Note the ternary operator as an alternative.
Design and Verification of AND Gate in Behavioural Level Modelling25:08
Explore behavioral level modeling of the and gate in Verilog HDL with hands-on design, test bench consistency, and the conditional operator and case constructs.
Design and Verification of AND Gate in Switch Level Modelling42:50
Design and verify an and gate in Verilog HDL using switch level modelling, applying hands-on techniques to practice verification.
Design and Verification of NOR Gate in Gate Level Modelling30:11
Design and Verification of NOR Gate in Dataflow Modelling14:47
Explore the NOR gate in data flow modeling using continuous assign statements. Compare with gate level modeling, discuss test benches, and demonstrate boolean and ternary implementations.
Design and Verification of NOR Gate in Behavioural Modelling30:26

Requirements

VS code or any eda playground usage should be known to start the course

Description

This course is designed for beginners eager to learn Verilog HDL for digital and VLSI design. The first five videos provide a comprehensive introduction, starting with the basics of hardware description languages and moving towards practical Verilog coding principles.

Introduction to Verilog HDL: Covers the fundamentals of what Verilog is, its history, applications in digital system design, design vs. verification, comparisons with VHDL and software languages, and the levels of abstraction in hardware design.
Basic Syntax and Data Types: Introduces the syntax of Verilog, key data types such as wire and reg, and how hardware constructs like gates and flip-flops map to Verilog structures.
Operators and Expressions: Explains the use of arithmetic, logical, and bitwise operators in Verilog coding along with examples to build simple combinational logic.
Module and Hierarchy Concepts: Details the structure of Verilog modules, port declarations, and how to instantiate modules to build hierarchical designs.
Behavioral Modeling and Conditional Statements: Explores behavioral modeling using always blocks, if-else conditions, case statements, and describes how to model sequential logic.

This course equips learners with foundational skills for Verilog programming, focusing on clarity, reusability, and practical digital system design concepts. It is ideal for students preparing for GATE or starting careers in VLSI design and verification.

Who this course is for:

Beginner who eagarly wanted to start the Verilog HDL with fully hands on Experience

Verilog HDL : Fully Hands on Learning Experience

What you'll learn

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Course content

Verilog HDL : Full hands on Learning Experience23 lectures • 9hr 50min

Verilog Full Pratical15 lectures • 6hr 52min

Requirements

Description

Who this course is for: