Introduction to RISC-V and RISC-V assembly programming

Name: Introduction to RISC-V and RISC-V assembly programming
Rating: 4.3 (14 reviews)

Introduction to RISC-V Instructions to start with RISC-V assembly programming for embedded systems.

Created byBenix Samuel Vincent Theogaraj

Last updated 7/2024

English

English [Auto],

What you'll learn

RISC-V Instruction Set Architecuture
RV32I Base Instructions
Development Environment Setup
Write Fibonacci Series generation & Bubble Sort in RISC-V assembly

Course content

6 sections • 17 lectures • 1h 48m total length

Introduction to the course1:20
Explore the open RISC-V instruction set architecture, its benefits, and the 38 to 40 base instructions, then set up hardware and software for RISC-V development and assembly.
Introduction to RISC, ISA and RISC-V14:18
Brief discussion about the RISC vs CISC based computer, Instruction Set Architecture and RISC-V organization

RISC-V Base Integer Instruction Set2:50
Discover the RISC-V base integer instruction set (rv32i), its 32 registers and program counter, and the mandatory load, store, control, and computational instructions.
Modularity and Extensibility of RISC-V ISA2:19
Explore the modular RISC-V ISA with extensions M and A, and 16-bit compressed instructions on a 32i core. Understand machine, supervisor, and user privilege levels, hypervisor support.
Customizability Support in RISC-V ISA1:55
Explain how RISC-V supports customization with vendor-defined instructions, like max, as long as the base ISA and extensions are compliant, and how the compiler, assembler, and debugger must support it.

Load Instructions7:06
Explore load and store instructions in RISC-V, moving data between memory and registers. Learn lui for 20-bit immediates and load word, load halfword (signed/unsigned), and load byte (signed/unsigned) variants.
Store Instructions2:37
Explain how store instructions transfer data from a source register into memory, using base plus offset addressing (up to 12 bits) to store byte, halfword, or word.
Arithmetic Instructions3:15
Explore arithmetic instructions in RISC-V assembly, including add immediate up to 12 bits, add, subtract, and the set less than variants in immediate and register forms, with unsigned options.
Test yourself on load, store and arithmetic instructions.
Alternate Register Names & Special X0 Register in RISC-V4:07
Explore alternate register names in RISC-V, focusing on the x0 hardware zero and how it enables deriving copy and move operations with addi, improving efficiency.
Logical & Arithmetic Shift Left & Right Instructions6:11
Explore logical and arithmetic shift left and right instructions in RISC-V assembly, using immediate and register-based forms, with 32-bit word width, sign extension rules, and practical register examples.
Test your understanding on shift instructions
Control Transfer Instructions8:11
Learn unconditional and conditional control transfer in RISC-V assembly, detailing jump and link (jal) with immediate or base-offset, target and return addresses, and 12-bit branch offsets.
Quiz on control transfer instruction

RISC-V Development Boards, Emulators, IDE and Toolchain6:51
Explore RISC-V development boards, emulators, and toolchains, compare open hardware options and on-board debuggers, and learn to set up with Freedom Studio and Spike.
RISC-V Pseudo Instructions & Assembler Directives2:50
Learn RISC-V pseudo instructions and assembler directives, mapping nop and jump offset to real ISA instructions. Understand how directives define .text and .data sections for code and data.
Introduction to Freedom Studio2:43
Explore the Freedom Studio IDE to create a Freedom SDK project for RISC-V assembly, and debug in emulation with memory and registers visible, stepping through code.

Fibonacci Sequence Generation in RISC-V Assembly12:45
Explore generating the Fibonacci sequence in RISC-V assembly by using a loop with branch, load, and store, storing results in memory from 0 and 1 onward.
Bubble Sort in RISC-V Assembly19:34
Demonstrates implementing bubble sort in RISC-V assembly to sort an array in ascending order, using outer and inner loops, addressing, and register usage.
Write risc-v assembly code to find the sum of diagonal elements of a 3x3 matrix

Requirements

If you are already an embedded developer or have knowledge about any processor, then this course will help you to jump start with RISC-V

Description

RISC-V is an open, modern Instruction Set Architecture (ISA) that is rapidly gaining adoption across the semiconductor, embedded systems, and processor design industries. Whether you're an embedded software engineer, firmware developer, or computer architecture enthusiast, understanding RISC-V has become an increasingly valuable skill.

This course is designed as a comprehensive beginner-friendly introduction to the RISC-V architecture. You'll learn what makes RISC-V unique, explore its standard instruction set extensions, and understand how it enables custom instruction extensions while maintaining compatibility with the standard ISA.

If you already have experience with any processor architecture or instruction set architecture (ISA) and want to get started with RISC-V, this course provides the perfect foundation. It covers everything you need to begin your RISC-V journey, including available development boards, simulators, toolchains, and the software environment required to start writing and executing RISC-V assembly programs.

The course provides an in-depth explanation of the RV32I Base Integer Instruction Set, including:

Load and Store instructions
Arithmetic and Logical instructions
Control transfer instructions
Conditional Branch instructions
Unconditional Jump instructions

Every concept is explained with practical examples to help you build a strong understanding of RISC-V assembly programming.

To reinforce the fundamentals, you'll implement real-world programming examples such as Fibonacci sequence generation and Bubble Sort entirely in RISC-V assembly. These hands-on exercises demonstrate how the RV32I instruction set is used to solve practical programming problems while introducing assembler directives, pseudo instructions, and important RISC-V programming conventions.

By the end of this course, you'll have a solid understanding of the RISC-V architecture, confidence in writing and debugging RISC-V assembly programs, and the practical knowledge needed to continue exploring advanced RISC-V topics and embedded software development.

Who this course is for:

Anyone who wants to quickly start with RISC-V assembly programming & jump into RISC-V ecosystem.
This is a beginner's course about RISC-V & RISC-V eco system.

Introduction to RISC-V and RISC-V assembly programming

What you'll learn

Explore related topics

Course content

Introduction2 lectures • 16min

RISC-V Instruction Set Architecture3 lectures • 7min

RV32I Base Instructions6 lectures • 31min

Introduction to RISC-V Development Environment3 lectures • 12min

Excerices2 lectures • 32min

M-Extension Instructions1 lecture • 10min

Requirements

Description

Who this course is for: