
Explore the open RISC-V instruction set architecture, its benefits, and the 38 to 40 base instructions, then set up hardware and software for RISC-V development and assembly.
Brief discussion about the RISC vs CISC based computer, Instruction Set Architecture and RISC-V organization
Discover the RISC-V base integer instruction set (rv32i), its 32 registers and program counter, and the mandatory load, store, control, and computational instructions.
Explore the modular RISC-V ISA with extensions M and A, and 16-bit compressed instructions on a 32i core. Understand machine, supervisor, and user privilege levels, hypervisor support.
Explain how RISC-V supports customization with vendor-defined instructions, like max, as long as the base ISA and extensions are compliant, and how the compiler, assembler, and debugger must support it.
Explain how store instructions transfer data from a source register into memory, using base plus offset addressing (up to 12 bits) to store byte, halfword, or word.
Explore alternate register names in RISC-V, focusing on the x0 hardware zero and how it enables deriving copy and move operations with addi, improving efficiency.
Explore logical and arithmetic shift left and right instructions in RISC-V assembly, using immediate and register-based forms, with 32-bit word width, sign extension rules, and practical register examples.
Explore RISC-V development boards, emulators, and toolchains, compare open hardware options and on-board debuggers, and learn to set up with Freedom Studio and Spike.
Introduce the RISC-V m extension and its four multiplication instructions: mul, mulh, mulhu, and mulhsu. Explain how they produce lower or upper 32-bit results and handle signed or unsigned operands.
RISC-V is an open, modern Instruction Set Architecture (ISA) that is rapidly gaining adoption across the semiconductor, embedded systems, and processor design industries. Whether you're an embedded software engineer, firmware developer, or computer architecture enthusiast, understanding RISC-V has become an increasingly valuable skill.
This course is designed as a comprehensive beginner-friendly introduction to the RISC-V architecture. You'll learn what makes RISC-V unique, explore its standard instruction set extensions, and understand how it enables custom instruction extensions while maintaining compatibility with the standard ISA.
If you already have experience with any processor architecture or instruction set architecture (ISA) and want to get started with RISC-V, this course provides the perfect foundation. It covers everything you need to begin your RISC-V journey, including available development boards, simulators, toolchains, and the software environment required to start writing and executing RISC-V assembly programs.
The course provides an in-depth explanation of the RV32I Base Integer Instruction Set, including:
Load and Store instructions
Arithmetic and Logical instructions
Control transfer instructions
Conditional Branch instructions
Unconditional Jump instructions
Every concept is explained with practical examples to help you build a strong understanding of RISC-V assembly programming.
To reinforce the fundamentals, you'll implement real-world programming examples such as Fibonacci sequence generation and Bubble Sort entirely in RISC-V assembly. These hands-on exercises demonstrate how the RV32I instruction set is used to solve practical programming problems while introducing assembler directives, pseudo instructions, and important RISC-V programming conventions.
By the end of this course, you'll have a solid understanding of the RISC-V architecture, confidence in writing and debugging RISC-V assembly programs, and the practical knowledge needed to continue exploring advanced RISC-V topics and embedded software development.