Digital Logic Design

Explore nand, nor, xor, xnor, and buffer gates; learn universal gate properties, three-state buffers with enable, high-impedance states, and how nand enables implementing all boolean functions.

Build truth tables for three inputs X, Y, Z to verify and, or, and not expressions and confirm Demorgan's theorem via left-right equality proofs.

Master binary logic fundamentals by using truth tables to evaluate and, or, and not operations on inputs X and Y, then translate boolean expressions into gate circuits.

Convert boolean expressions to SOP by mapping A, B, C, D and primes on a Karnaugh map to identify minterms and sigma terms such as 1,3,7,9,11,12,13,15.

Demonstrate Karnaugh maps for simplifying boolean expressions using sum of products and product of sums (POS), with minterms and maxterms, and two-level circuits using and gates.

Transfer data from the truth table into three-variable and four-variable Karnaugh maps, group adjacent ones, wrap corners, and derive minimized msp expressions using gray code.

Explore the five-variable Karnaugh map with 32 cells and wrapping adjacency to simplify Boolean functions, using don't care cases to form larger groups and convert between minterms and maxterms.

Explore Karnaugh maps for two- and three-variable functions by mapping minterms and maxterms, applying gray code, and grouping ones in powers of two to simplify expressions.

Learn step-by-step boolean expression simplification using axioms, distributive and De Morgan's laws, then explore minterms and the sum of minterms (sigma notation).

Explore the sum of minterms and the product of maxterms forms in digital logic design, implementing two-level pos circuits with literals, or gates, and a final and gate.

Explore Karnaugh maps for two and three variables, converting minterms from truth tables into maps, using gray code, identifying adjacent blocks, and forming power-of-two groups to simplify expressions.

Transfer minterms from the truth table into the three-variable and four-variable Karnaugh maps, then form the largest adjacent groups of ones, wrapping corners as needed, to simplify into MSP.

Master hierarchical design of combinational logic using blocks and interconnections to manage complex circuits, and reuse three-input function blocks and xors to implement parity with schematics built from nand gates.

Explore design flows for combinational circuits using CAD tools and hardware description languages, then build a two-bit comparator with truth tables, Karnaugh maps, and gate-level realization.

Explore combinational design by converting BCD to excess three and to a seven segment decoder, using truth tables, Karnaugh maps, and simplified equations to drive led displays.

Use a 3-to-8 decoder and an or gate to implement the function, mapping inputs A, B, C to S0–S2, enabling the decoder and or-ing the selected outputs.

Explore how decoders convert binary inputs into a single active output, from 1-to-2 to 3-to-8, using truth tables, enable options, and minterm generator.

Explore encoders as the inverse of decoders, with n inputs and 2^n outputs producing the binary code of the active input, including octal-to-binary and priority encoders.

Explore how multiplexers act as switch selectors routing one of many inputs to a single output using select lines, enabling you to implement logic functions and full-adder operations.

Design a 4-to-16 decoder by cascading five 2-to-4 decoders with enable inputs, wiring s0 and s1 to all decoders and using the most significant bits to enable the appropriate decoder.

Analyze the inner circuit of a 4-to-1 multiplexer to see how S1 and S0 select inputs I0–I3 and determine the output waveform Y for the given input pattern 1010.

Design a 4-to-16 decoder with enable using five 2-to-4 decoders, wiring s0 and s1 as the least significant inputs and s2 and s3 as the most significant to produce q0–q15.

Design an excess-3 to binary decoder by using unused combinations as don't care, build four Karnaugh maps for W, X, Y, Z, and derive simplified expressions.

design a three-input, one-output combinational circuit that outputs 1 for minterms 0, 1, and 2 using a Karnaugh map; implement with nand gates via De Morgan transformations.

Trace the inner circuit of a 4-to-1 multiplexer to determine the output waveform Y from inputs I0–I3 based on select lines S1 and S0.

Explore how arithmetic functions and circuits perform binary addition using half adders and full adders, cascade them into a four-bit adder, and understand carry, sum, and overflow in unsigned numbers.

Explore how a 4x4 multiplier uses and gates to form partial products, shift left, and add with an adder to produce the final product.

Design a 4-bit magnitude comparator to determine equal, less than, and greater than for two 4-bit numbers using a divide-and-conquer approach, building a one-bit comparator and combining outputs.

Design a 4-bit magnitude comparator using xor and xnor for equality, then use four-input and/or gates to implement greater-than and less-than conditions across A3–A0 and B3–B0.

Learn how sequential circuits store information with latches built from nor and nand gates, including sr and d latches, set and reset operations, and the corresponding state diagrams.

Learn how sequential circuits use clocks and flip-flops to control memory and timing, from latches to D, JK, and T flip-flops, including master-slave designs and timing diagrams.

Explore sequential circuit analysis by comparing Moore and Mealy models, deriving next states from boolean expressions and flip-flop inputs, and visualizing state diagrams for two flip-flop systems.

analyze a sequential circuit with two jk flip-flops by deriving j and k equations, building the state table, and drawing the state diagram to determine next states and output.

Design synchronous sequential circuits in digital logic design with flip flops and combinational gates, using a 1001 sequence recognizer and JK- and D-flip-flop implementations.

Explore how registers use flip flops to store n bits of binary information and how loading, feedback, and multiplexers determine data paths.

Shift registers use flip-flops with a common clock to move data serially from left to right, contrasting with parallel loading; four-stage examples demonstrate serial transfer from A to B.

Explore a four-bit universal shift register that supports parallel load, read, and left or right shift via select lines and multiplexers, including serial input and serial out.

Explore how a serial adder uses two shift registers and a single full adder to add binary numbers bit by bit, propagating carry with each right shift.

Explore synchronous and asynchronous counters built from flip-flops, featuring up/down operation, state tables, excitation equations, and practical designs with serial and parallel gating.

Design a three-bit counter with two modes: normal counting 0–7 and even-number counting 0,2,4,6, controlled by a single input, with state tables, t flip-flops, and Karnaugh-map optimization.

This ripple counter analysis uses three flip flops clocked on falling edges to show starting from zero, a repeating sequence of zero, one, four, five, two, three, six, seven.

Explore a ripple counter using three t flip-flops, with Q0 and Q2 sharing clocks and counting on falling edges. Follow the sequence from zero to seven and back.