VLSI/FPGA Design P2: Verilog for Design and Verification

Learn Verilog, a hardware description language for digital circuits, covering module, initial blocks, RTL versus testbench coding, and simulation with Verilator.

Learn Verilog basics for describing combination logic, including module definitions, net and variable types, continuous and procedural assignments, and testbench simulation with gtkwave and Verilator.

Describe d flip-flops in Verilog, covering synchronous and asynchronous reset, posedge and negedge triggers, non-blocking versus blocking assignments, testbench generation, and waveform verification with Verilator and GTKWave.

Explain how Verilog reg signals power up with unknown values and how Verilator uses two-state semantics, unlike four-state simulators like ModelSim or VCS, with focus on synchronous reset.

Master common Verilog syntax: wait for posedge clock, repeat cycles, system tasks, and signal declarations; explore vectors, arrays, signed types, bitwise to arithmetic operators, and testbench considerations.

Explore Verilog if-else and case statements to implement muxes and priority logic, with synthesis rules to avoid latches and ensure complete default branches.

Explore sign extension and one hot decoder in Verilog, showing signed versus unsigned arithmetic, extension techniques, one hot decoding methods, and synthesis directives for reliable design.

Explore small but useful Verilog circuits, including DFFs with asynchronous and synchronous resets, edge detectors, counters with enable, and shift registers, with diagrams, RTL code, and waveform verification.

Identify and avoid common Verilog mistakes in combinational logic: incomplete sensitive lists, incomplete if-else or case, latch, combinational loops, and multi-driven signals; use default values and lint tools like Spyglass.

Design and verify a Verilog 8x8 z-scan function that outputs raster IDs in z-order. Implement start-of-block timing, bank-to-bank transfer constraints, and automated test bench validation.

Examine reference Verilog code for a z-scan design, detailing a 64-cycle counter, raster and SOB signals, and two implementations, supported by a mixed fixed and random testbench for verification.

Demonstrates organizing a Verilog project with three directories—code, sensitive code, and pattern for simulation models and testbenches—and a makefile to run simulations, including a validator option to disable lint errors.

Explore finite state machines, mealy and moore outputs, and defining states and transitions with Verilog's three-block style: state register, transition logic, and output logic.

Explore finite state machine coding styles for sequence detectors in Verilog, comparing three-block, two-block, and one-block designs, noting latency, register timing, and flexibility of the state and output logic.

learn to implement a 7-bit sequence detector using cascaded shift registers and data comparison, enabling overlapping sequences and an example of 1011 detection.

Explore Verilog function and task syntax, including definitions, inputs and return value, and the key differences in timing, wait statements, and module signal access for testbenches.

Analyze testbench for a sequence detection function by using a stimulus task to compare two implementations, and review model and dut architecture, eight-cycle shift, and fixed or randomized patterns.

Explore how Verilog executes in software, covering simulation times, non-blocking and blocking assignments, and same-time ordering, with guidance to avoid undefined behavior across blocks when modeling registers.

Develop a Verilog based test bench for a DUT with stimulus, a reference model, and a checker to automate verification using SystemVerilog and UVM for high test coverage.

Explore Verilog generate and parameter constructs to create scalable hardware, using genvar for loop unrolling at rtl compile time, and parameterized modules such as sram designs and conditional logic.

Decompose IP blocks into control and data path segments to design large-scale hardware. Use top-down methodology with submodules, implement in Verilog, and contrast with bottom-up approaches.