Udemy
    •  
    •  
    •  
    •  
    •  
    •  
    •  
    •  
Subscribe
Turn what you know into an opportunity and reach millions around the world.
Learn More
Your cart is empty.
Keep shopping
VLSI/FPGA Design P2-S3: Verilog for Design and Verification
Rating: 4.1 out of 5(13 ratings)
853 students

VLSI/FPGA Design P2-S3: Verilog for Design and Verification

Consistency between circuit diagram, RTL code and waveform
Created bySKY SiliconThink
Last updated 3/2025
English

What you'll learn

  • Common used Verilog syntaxes for design and verification
  • Descript combination logic (basic logic gates, MUX, decoder, one-hot decoder)
  • Descript sequential logic (DFF with sync/async reset, ounter, edge detect, shift registers, sequence check, sync_fifo)
  • Design finite state machine (FSM)
  • Write testbench
  • Using Verilator and GTKwave to debug a design
  • Common mistakes for synthesis (incomplete sensitive list, latch, multi-driven, combination logic loop)
  • Practice time: z-scan, complex sequence check (FSM)

Course content

1 section • 5 lectures • 1h 54m total length

  • Introduction3:38

    Introduces Verilog as a hardware description language, covering IP and IC design flow, combination and sequential logic, finite state machines, and testbenches verified with Verilator and Gtkwave.

  • Verilog Syntanx: Declare and Operators37:49

    Learn Verilog syntax essentials, including wait with posedge and negedge, repeat, system tasks, nets and variables, vectors, arrays, concatenation, bit selection, and operators.

  • if-else if-else and case statement37:25

    Explore Verilog's if-else and case statements, showing how to implement and synthesize combinational logic for multiplexers (4-to-1, 8-to-1) and decoders, with emphasis on priority, default branches, and RTL consistency.

  • sign extension and one-hot decoder33:39

    Explore sign extension and one-hot decoding in Verilog, learning sign versus zero extension for two's complement numbers, and synthesize directives like full case and parallel case for one-hot decoders.

  • Promotion: VLSI/FPGA Design Resume Project: 2D DMA Controller with APB+AXI Inf.2:19

    Design a 2D DMA controller IP block to enable data movement between system addresses, demonstrated in an FPGA project with a 2D game.

Requirements

  • Basic knowledge of digital fundamental
  • Basic C or C++ programing language

Description

The speech isn't fluent, please turn on the subtitle to help your understanding.


Quick master through examples and coding exercises, in videos less than 10 hours. After study, you can have the ability of consistency between circuit schematic, Verilog code and waveform. That’s given anyone of them, you can figure out the other two. In this chapter (will be divided to several free sections), I’ll explain:

1: Digital IP/IC design flow;

2: Quick review of digital fundamental

3: Install Verilator and GTKwave

4: Common used Verilog syntax for design and verification

5: Design combination logic(basic gates, MUX, decoder, one-hot decoder)

6: Design sequential logic(sync-DFF, async-DFF)

7: Design small but useful block(counter, edge detect, shift registers, sequence check, sync_fifo)

8: Design FSM(finite state machine)

9: Design basic testbench

10: Common mistakes for synthesis(incomplete sensitive list, latch, multi-driven, combination logic loop)

11: Practice time: design and verify z-scan and complex sequence check(FSM)


This is chapter 2, section 3 of whole Digital IC and FPGA design course.

In the whole course, I will introduce fundamentals of digital IC and FPGA design, with 12+ coding exercises and 3 course projects.

Theory part: MOS transistor -> logic cells -> arithmetic data path -> Verilog language -> common used HW function blocks and architecture -> STA -> on-chip-bus(APB/AHB-Lite/AXI4) -> low power design -> DFT -> SOC(MCU level).

Function blocks and architecture: FSM, pipeline, arbiter, CDC, sync_fifo, async_fifo, ping-pong, pipeline with control, slide window, pipeline hazard and forward path, systolic.

Project: SHA-256 algorithm with simple interface, SHA-256 with APB/AXI interface, 2D DMA controller with APB/AXI interface.

After explaining of each HW architecture, I will give you a coding exercise, with reference code. Coding difficulty will begin from several lines to fifty lines, more than 100 lines, then around 200 lines. While the final big project will be 1000+ lines.

I suppose these should be essential knowledge and skills you need master to enter this area.

I will try my best to explain what-> how-> why and encourage you to do it better in this course.


Please browse to my homepage on Udemy to obtain information about each chapter of this course.

Who this course is for:

  • Anyone who wants to study Verilog and digital IC/FPGA design

Report abuse