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30-Day Money-Back Guarantee
IT & Software Hardware FPGA

Digital System Design with High-Level Synthesis for FPGA

Combinational Circuits
Highest Rated
Rating: 4.9 out of 54.9 (28 ratings)
192 students
Created by Mohammad Hosseinbady
Last updated 11/2020
English
English
30-Day Money-Back Guarantee

What you'll learn

  • Designing combinational logic circuits with C/C++ language using the HLS approach
  • Understanding the basic concepts of High-Level Synthesis (HLS)
  • Using HLS concepts for designing combinational logic circuits
  • HLS design flow for FPGAs
  • Working with Xilinx Vivado-HLS and Vivado suite Toolsets
  • How to generate RTL hardware IPs using Vivado-HLS
  • Writing C-testbench in HLS
  • Implementing two exciting projects with HLS

Requirements

  • Understanding the basic concepts of C/C++ coding
  • Understanding the basic concepts of logic operators (e.g., AND, OR, XOR, SHIFT )
  • BASYS3 evaluation board
  • Xilinx Vivado-HLS and Vivado (download Vivado HLx 2019.2: WebPACK and Editions for Windows or Linux)

Description

This course is an elementary introduction to high-level synthesis (HLS) design flow. The target of the course is describing, debugging and implementing combinational logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog).

It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. This course is the first of its kind that builds the HLS design flow and skills along with the digital logic circuit concepts from scratch. Along the course, you will follow several examples describing the HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches.

This course is the first of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on combinational circuits, the other courses in the series will explain how to use HLS in designing sequential logic circuits, algorithm acceleration, and hybrid CPU+ FPGA heterogeneous systems.

Who this course is for:

  • Hardware engineers
  • Software engineers who are interested in FPGAs
  • Lecturers, researchers, professors who want to use FPGA-based HLS in lectures, courses or research
  • Digital Logic enthusiasts

Featured review

Dung-Yi Chao
Dung-Yi Chao
24 courses
4 reviews
Rating: 5.0 out of 54 months ago
This course is well structured. The slides and animation are very clear too. You can follow the instructor without any problem. The instructor will respond to your question very soon and so much explanation. Looking forward to the next series of courses.

Course content

14 sections • 110 lectures • 7h 47m total length

  • Preview05:08
  • Preview05:11

  • Introduction
    02:06
  • Features and Applications
    02:14
  • Design Approach
    04:20
  • FPGA Platform vs CPU Platform
    05:46
  • FPGA Basic
    03:54
  • LUT
    03:29
  • Flip-Flop And Other Elements
    04:40
  • Basys3 FPGA Development Board
    05:05
  • Why HLS?
    04:17
  • Hardware and Software Analogy
    05:05

  • Introduction
    02:10
  • Vivado-HLx
    04:49
  • Vivado and Vivado-HLS
    03:55
  • Install Vivado-HLx
    03:41
  • Test Installation
    06:39

  • Introduction
    03:20
  • Output Configuration
    02:43
  • Controller Concept
    02:25
  • HLS Design Overview
    02:53
  • HLS Design Flow
    05:45
  • HLS C/C++ Design
    04:04
  • HLS Ports
    03:36
  • HLS LAB
    08:53
  • Vivado
    04:34
  • Vivado LAB
    07:24
  • Basis3 Board
    04:19
  • Exercises
    00:44

  • Introduction
    02:36
  • Configuration
    01:44
  • Controller Concept
    01:59
  • HLS Ports
    04:32
  • HLS LAB
    04:17
  • Vivado LAB
    06:10
  • Exercise
    00:43

  • Introduction
    02:53
  • Definition
    02:58
  • Logic Gates
    03:32
  • Propagation Delay
    04:53
  • Binary Adder Delay
    03:46
  • Combinational Circuit in HLS
    04:32
  • Combinational Circuit in Vivado-HLS
    04:54
  • Combinational Circuit in Vivado
    06:19
  • Functions
    06:10
  • Dataflow
    05:33
  • Traffic Light
    06:30
  • Traffic Light-Vivado-HLx
    10:14
  • Exercises
    00:41

  • Introduction
    02:09
  • Definition
    03:25
  • Simulation Flow
    03:29
  • HLS Testbench Coding
    04:00
  • Vivado HLS
    08:10
  • Exercises
    00:15

  • Introduction
    03:16
  • Native Datatypes
    03:13
  • Synthesis
    06:54
  • Bit Precision: Declaration
    04:30
  • Bit Precision: Initializing
    03:59
  • Bit Precision: Assignment
    05:08
  • Bit Precision: Print
    02:36
  • Bit Precision: Bitlevel
    03:49
  • Bit Precision: Bitwise Logical Operators
    03:23
  • Bit Precision: Shift/Rotate
    02:21
  • Exercises
    00:29

  • Introduction
    02:16
  • Definition
    02:28
  • Multiplexer
    02:13
  • Multiplexer: General Case
    03:55
  • HLS
    03:49
  • Encoder/Decoder
    04:46
  • Leading One
    02:58
  • LAB
    15:42
  • Exercises
    00:26

  • Introduction
    03:35
  • Definition
    02:32
  • 7-Segment Codes
    01:31
  • Basys3
    02:42
  • One Digit
    02:53
  • BCD Code
    02:25
  • BCD TO 7-segment: Div/Mod
    05:34
  • BCD TO 7-Segment: Double Dabble
    04:50
  • Two Digits
    03:39
  • Preview14:23
  • Exercises
    00:26

Instructor

Mohammad Hosseinbady
PhD
Mohammad Hosseinbady
  • 4.9 Instructor Rating
  • 28 Reviews
  • 192 Students
  • 1 Course

Mohammad Hosseinabady received the PhD degree in computer engineering. He has been teaching electronics and computer courses in several universities for more than ten years. He is currently working on high-level synthesis for FPGA. His goal is to make advanced reconfigurable technologies more accessible for everyone who may not have in-depth knowledge of FPGAs and the traditional hardware design methodologies. His research interests include high-level reliability and testability, reconfigurable architectures, dynamic resource management, and runtime power management. He has published several papers on these topics in IEE, IEEE and ACM transactions, journals and conference proceedings.


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