High-Level Synthesis for FPGA, Part 1-Combinational Circuits

Explore the essentials of starting with high-level synthesis for FPGA, outlining the FPGA structure, design flow, and the required C/C++ skills, plus why HLS suits FPGA design.

Explore how FPGA provides programmable, reconfigurable hardware that delivers high speed, low power, faster time to market, and real-time capabilities across aerospace and defence, automotive, AI inference, 5G, and more.

Explore the FPGA design flow from gate-level to RTL and high-level synthesis. See how HLS using C/C++ automates timing and resources mapping, keeping HLS as a mainstream approach.

Compare the fpga and cpu platforms to show sequential execution on the cpu and parallel execution on the fpga when a c/c++ program is translated into hardware modules by synthesis.

Learn the basic FPGA architecture and why HLS abstracts internal structures, covering the application and configuration layers, bitstreams, and synthesis tools that map designs to LUTs and FFs.

Discover how an FPGA look-up table implements combinational logic using a configuration memory and multiplexed cells. See how a 2-input LUT uses a multiplexer to select the output.

Explore how flip-flops provide temporary storage for sequential logic in FPGAs, alongside LUTs for combinational logic, CLBs, slices, and memory blocks like BRAM and DSP elements that enhance arithmetic performance.

Explore the Basys 3 fpga development board, powered by an Artix-7, with extensive resources and i/o for implementing combinational and sequential designs and programming modes.

learn why hls and fpgas matter for modern compute, delivering lower energy, higher performance, and shorter time to market for data-heavy image and video processing on mobile, edge, and cloud.

High-level synthesis reveals the analogy between a software C function and a hardware module, highlighting parallel hardware bodies, input/output ports, interfaces, and compiler directives.

Build a simple lab environment to implement high-level synthesis concepts with basys3, a PC, and the Xilinx vivado-hlx toolset, with installation, setup, and a five-lecture overview.

Explore the Xilinx Vivado-HLx toolset for describing, simulating, debugging, and synthesizing designs into FPGA bitstreams, with emphasis on C/C++ high-level synthesis and co-simulation for cycle-accurate verification.

Explore how Vivado-HLS converts C/C++ designs to HDL and how Vivado yields the final bitstream, via design capture, C-simulation, HLS synthesis, co-simulation, and IP export.

Learn to install Vivado HLx for FPGA development: create a Xilinx account, download Vivado HLx WebPACK for Windows or Linux, install, and add Basys 3 board definitions from Digilent.

Test the lab environment for HLS design by setting up and validating Xilinx Vivado-HLS, Vivado, and the Basys-3 board, including creating a project, synthesizing, exporting RTL, and programming the board.

Learn to describe a simple LED controller in C for high-level synthesis, and implement it on the Basys-3 board using Vivado-HLS and Vivado, following the HLS design flow.

Drive the Basys 3 board's 16 user LEDs from FPGA pins through 330-ohm resistors. Turn on an LED by applying logic high and prepare for LED controller design in HLS.

Explore how a simple HLS-driven logic circuit drives leds on a Basys3 board, linking an inside-FPGA function to pin constraints for a complete design.

Outline the hls design flow with vivado-hls, focus on coding in c/c++, port interfaces, and ip generation, then integrate ip, apply constraints, and generate the bitstream.

Explore the c/c++ based design flow in vivado-hls, covering hardware-focused coding, suitable data types, c-simulation, rtl-co-simulation, and the role of pragmas and synthesis in producing hdl ip.

Describe how a C/C++ function models a hardware module in HLS. Map LED outputs, inputs, and inouts with interfaces and directives.

Describe how to add port interfaces to function arguments in a C/C++ HLS description, using pragma directives to assign input, output, and inout ports and their interfaces.

Learn to describe a hardware module in C/C++ using Vivado-HLS, create a project, add a source file, perform synthesis, and export RTL IP for the Basys3 board.

Learn how to convert a hardware IP from Vivado-HLS into an FPGA bitstream using the Vivado toolset, importing the IP and applying I/O constraints to map led[7:0] to FPGA pins.

Create a Vivado project and block design to integrate Vivado-HLS generated IP, drive an 8-bit led output on the Basys3 board, and generate the FPGA bitstream with XDC constraints.

Program the target FPGA by downloading the bitstream with Vivado, using hardware manager and hardware server, following five steps: connect the board, open project, open the target FPGA, and program.

Explore basic input mechanisms on the Basys3 board by linking slide switches to LEDs using an HLS flow, Vivado, and bitstream generation to program and test the design.

Explore the Basys3 FPGA's basic input/output configuration, using 16 switches and 16 LEDs to read switch states and drive LEDs, and learn the FPGA I/O pin mappings.

Unpack the controller concept in high-level synthesis for FPGA, detailing a five-part switch-to-led design described by an HLS C function with port interface constraints.

Practice defining hls ports and interface synthesis in vivado-hls by connecting an 8-bit unsigned char input/output through a top-function with per-argument interfaces and mode choices, including ap_none and ap_ctrl_none.

Explore high-level synthesis with Vivado-HLS by building a basic input-output LED controller, defining ap_ctrl_none and ap_none interfaces, synthesizing, and exporting RTL hardware IP for Basys3.

Integrate the generated RTL-IP into a Vivado project to generate the final FPGA bitstream for the Basys3 board, including constraints and hardware manager programming.

Introduce combinational circuits in high-level synthesis, showing how logic circuits process input data with algorithms, producing outputs in a propagation delay, and laying groundwork for modeling with dataflow graphs.

Define combinational circuits as logic whose outputs depend only on current inputs, with no memory, and learn how they synthesize arithmetic and logical expressions, controllers, and data transmission.

Explore the fundamental logic gates—and, or, not, nand, nor, xor, xnor—and how they form combinational circuits, including half-adder and full adder, with De Morgan's laws and gate delay.

Explore propagation delay in combinational circuits, define gate propagation delay and the critical path that determines circuit delay, and explain how HLS aims to reduce delay and improve performance.

Analyze the propagation delay of an n-bit ripple carry adder built from full-adders using gate delays, showing a 2N ns worst path. Explore estimating delay with Vivado-HLS for high-level designs.

Describe a three-input, one-output combinational circuit in hls using C/C++ operators or bitwise logic, set ap_none interfaces, synthesize with vivado-hls, and interpret timing and resource reports.

Learn to synthesize a simple combinational circuit in Vivado HLS using the Vivado IDE, creating a project and reviewing the analysis perspective for timing and resource details.

Translate the HLS combinational circuit into a hardware IP, generate the Vivado bitstream, and program the Basys3 board using constraints and RTL-IP design steps.

Examine how functions describe logic circuits in hls and how Vivado-HLS translates c/c++ functions into rtl hardware. Learn top-level interfaces, inlining, and pragmas to control synthesis while avoiding system calls.

Explore dataflow modeling of combinational circuits using directed acyclic graphs and acyclic dataflow graphs. See how high-level synthesis unrolls loops to convert cyclic dataflow into acyclic graphs for synthesis.

Design a traffic light controller from combinational rules using four sensors U, L, D, R. Implement EW and NS outputs with gate logic and C functions for HLS on Basys3.

Map the traffic_light HLS controller to the Basys3 board using Vivado-HLS, create a traffic_light-vhls project, add traffic_light.cpp and traffic_light.h, and synthesize a combinational LUT-based design.

Explore how high-level synthesis uses simulation to verify functional and timing correctness in early hardware design, including C software simulation, testbenches, and hardware/software co-simulation in HLS.

Explore simulation-based verification in high-level synthesis by building a testbench that generates inputs, applies them to the design and the golden model, and compares the outputs.

Explore the Vivado-HLS simulation flow from C/C++ design and test benches through C simulation, HLS synthesis, and C/RTL cosimulation to verify timing and functionality before generating the IP.

Explore writing a Vivado-HLS test bench that uses main() as the top bench, generates 8-bit inputs, calls the design, compares outputs to the golden model, and returns 0 on success.

Use the Vivado HLS IDE to perform C and C++ simulations for a three-input, one-output combinational circuit. Build testbenches, run co-simulation, and verify results with the waveform viewer.

Explore data type options in high-level synthesis for hardware design, from 8-bit built-in C/C++ types to arbitrary-precision bit-width types in Vivado-HLS for signals and ports.

Explore how Vivado HLS handles C/C++ native data types, including bool, char, int, and float, with bit-size examples like 8-bit char, 32-bit unsigned long, and 64-bit long long during synthesis.

Learn how high-level synthesis maps code variables to hardware in combinational circuits, with optimised variables bound to wires and memories avoided; includes Boolean and arithmetic examples.

Define bit-accurate data types with arbitrary sizes using Vivado HLS's C++ library, including ap_int.h and the ap_int/ap_uint templates that support 1 to 1024 bit widths.

Initialize arbitrary precision variables in C++ using class constructors and overloaded assignment, supporting up to 64-bit values and string initializers with radix 2, 8, 10, or 16.

Learn to assign values to arbitrary-precision variables, handle wider and narrower bit-widths with sign-extension, zero-extension, and truncation in C/C++, and Vivado-HLS.

Explore printing arbitrary-precision values in HLS simulations using C++ streams; note that printing is not synthesizable and used for C-simulation only, with to_string, c_str conversions, and std::oct, std::dec, std::hex.

Explore common bit-level operations in Vivado-HLS, including width calculation with length(), bit concatenation with concat and overloaded comma, bit selection with square brackets, and range selection with rang.

Explore bitwise logical operators in hardware design, including OR, AND, XOR, and inverse, with unsigned or signed operands, width rules, and bitwise reductions and reversals in Vivado HLS.

Describe bit shifting and rotating in Vivado-HLS using overloaded C/C++ operators for arbitrary-precision types, including rrotate and lrotate. Note unsigned and signed shifts; a negative RHS reverses signed shift direction.

Explore conditional statements in high-level synthesis (HLS) and how software decisions map to hardware using multiplexers to implement if-then-else and switch-case constructs as combinational circuits.

Describe how conditional statements translate across software and hardware, highlighting hypothesis and conclusion as core decision making, and how if-then structures, switches, and multiplexers implement these conditions.

Explore the multiplexer as the hardware decision unit, showing how data and select inputs route either a or b through basic gates, and discuss generalised mux forms for design.

Explore the generalized form of multiplexers in high-level synthesis, including wide bit-width inputs and selection logic. See how combinational circuits preprocess data and control signals to implement decision-making.

Explore three HLS techniques to describe a 2x1 multiplexer, using the ternary operator, complete if-else, and switch-case—emphasizing combinational design and the need for proper select logic.

Explore how encoders and decoders transform data formats using combinational logic in high-level synthesis, with octal-to-binary examples and switch-case implementations in HLS.

Design a leading-one detector as a 9-bit combinational circuit using a 10x1 multiplexer and four 2-by-1 multiplexers, with HLS if-else logic, returning -1 for zero, mapped to Basys3 FPGA.

Explore using Vivado-HLS to implement a leading_one circuit on Basys 3, including creating a project, adding design and testbench files, C-simulation, and synthesis to obtain a combinational RTL circuit.

Explore how to drive a 7-segment display in high-level synthesis for an FPGA, using data and control signals in a multiplexed, combinational approach on Basys3 hardware.

Explore the seven segment display structure, including common anode and common cathode configurations, control and data signals, and how digits like three and four are driven.

Discover seven-segment codes for digits 0-9 on a common anode display, including example codes such as 11000000 for 0 and 11111001 for 1, stored in a C++ array.

Explore how to drive Basys3 7-segment displays using high-level synthesis, focusing on combinational circuit design, the four displays, their 12 pins, control lines, and shared 8 data signals.

Demonstrate a C function that drives a single 7-segment display by encoding a decimal digit through a multiplexer, with ap_none interfaces and HLS concepts.

Learn how binary numbers are converted to decimal-friendly BCD codes for display on 7-segment displays. Compare packed and unpacked BCD representations and how conversion enables 7-segment output in high-level synthesis.

Design a four-digit binary-to-bcd combinational circuit using a get_digit approach and loop elimination for synthesis. Explore modulus handling with a dedicated divider and introduce the doble-dabble method for efficient conversion.

Explore implementing a binary to two-digit BCD converter using the double dabble algorithm (shift and add-3) in HLS, with a 16-bit variable and a binary2bcd top function.

Convert a binary input under 100 to a two-digit BCD and display it on two Basys3 7-segment displays; use push-buttons to select the active digit and implement with high-level synthesis.

Synthesize a single-digit 7-segment controller with vivado-hls, generate the fpga bitstream, and verify on the basys3 board using test benches, c-simulation, and rtl-c co-simulation.