High-Level Synthesis for FPGA, Part 3 - Advanced
What you'll learn
- Using Multi-Cycle design flow to develop sequential circuits in HLS.
- Implementing stream communication and computation in HLS
- Using FIFO as the synchronisation mechanism between to connected module
- Learning how to use an array variable inside an HLS code
- Connecting and AND HLS IP to BRAMs in a Vivado project
- Working with pointers in HLS
- Working with AXI protocol in HLS
- Loop pipelining optimisation in HLS
- Loop unrolling optimisation in HLS
- Loop flattening optimisation in HLS
- Loop rewinding optimisation in HLS
- Working with the HLS-Stream library in HLS
- Handshaking protocol and interfaces in HLS
Requirements
- Understanding the basic concepts of C/C++ coding
- Understanding the basic concepts of logic operators (e.g., AND, OR, XOR, SHIFT )
- “High-Level Synthesis for FPGA, Part 1-Combinational Circuits” Udemy course
- “High-Level Synthesis for FPGA, Part 2 - Sequential Circuits” Udemy course
- BASYS3 evaluation board
- Xilinx Vitis-HLS and Vivado (download Vivado ML Edition or Vivado Design Suite - HLx Editions for Windows or Linux)
Description
This course covers advanced topics in high-level synthesis (HLS) design flow. The goals of the course are describing, debugging and implementing logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog). The HLS is recently used by several industry leaders (such as Nvidia and Google) to design their hardware and software platforms. The HLS design flow is the future of hardware design. It quickly becomes a must-have skill for every hardware or software engineer keen on utilising FPGAs for their exceptional performance and low power consumption.
This course is the first to explain the advanced HLS design flow topics. It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. Throughout the course, you will follow several examples describing HLS concepts and techniques. The course contains numerous quizzes and exercises to practice and master the proposed methods and approaches.
This course is the third of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on multi-cycle design, advanced design, and optimisation techniques in HLS, the other courses in the series explain how to use single-cycle design techniques to develop combinational and sequential logic circuits in HLS.
Who this course is for:
- Hardware engineers
- Software engineers who are interested in FPGAs
- Lecturers, researchers, and professors who want to use FPGA-based HLS in lectures, courses or research
- Digital Logic enthusiasts
Instructor
![Mohammad Hosseinbady](data:image/svg+xml,%3Csvg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 64 64"%3E%3C/svg%3E){kind=avatar}
- 4.5 Instructor Rating
- 475 Reviews
- 2,314 Students
- 4 Courses
Mohammad Hosseinabady received the PhD degree in computer engineering. He has been teaching electronics and computer courses in several universities for more than ten years. He is currently working on high-level synthesis for FPGA. His goal is to make advanced reconfigurable technologies more accessible for everyone who may not have in-depth knowledge of FPGAs and the traditional hardware design methodologies. His research interests include high-level reliability and testability, reconfigurable architectures, dynamic resource management, and runtime power management. He has published several papers on these topics in IEE, IEEE and ACM transactions, journals and conference proceedings.