High-Level Synthesis for FPGA, Part 3 - Advanced

Set up the AMD Xilinx V Vado ML toolset on a Windows or Linux host, connect an FPGA base board, and learn the HLS design flow from code to bitstream.

Install and configure Xilinx Vivado tools on Windows using the unified installer, download Vado ML and Vivaldi board files, and test with a basic output design on a connected board.

Learn to install the Vivaldi and Vitus toolsets on Ubuntu, with or without VirtualBox, set up dependencies, and program the FPGA using Xilinx tools and USB.

Explore the multi cycle design approach as an alternative to single cycle designs, addressing data and control dependencies, resource limits, and asynchronous data transfers through handshaking.

Explain the single cycle and pipeline design approaches with an initiation interval of one, noting high performance and low latency. Address synchronization and handshaking with valid signals across modules.

Compare multi cycle designs with scii-based designs, explaining how latency or initiation interval affects data reception, safe data exchange between modules, and when to relax constraints to avoid input loss.

Demonstrate a multi-cycle design counting from zero to a max value, driving a seven-segment display, with a static state, clock, and reset, and a valid handshake to prevent input loss.

Explain the handshaking mechanism between two connected modules for negotiating data transfer. Use valid and acknowledge signals to implement one-way or two-way synchronization and address missing input data.

Explore a simple multi-cycle design using the ap_vld valid signal protocol to mark data as valid, enabling handshaking for an up-counter example.

explore the acknowledge handshaking signal to prevent missing input data, detailing the AP underscore ack protocol coordinating input and output ports for an up counter and pulse generator.

Implement a two-way handshaking protocol between sender and receiver using the data port valid and acknowledge signals, demonstrated with the AP_s port level IO interface.

Learn block-level handshaking for FPGAs, compare chain, s, and none API modes, and understand AP start, AP done, AP idle, and AP ready signals for pipelined and non-pipelined designs.

Explore streaming protocols in HLS to synchronize two multi cycle modules on FPGAs. Learn to implement streaming data with FIFO memory and pointer variables, using FIFO IP cores for connections.

Explain extreme data synchronization between two FPGA modules using FIFO-based streaming and handshaking, where the sender pushes data, the receiver fetches it, and FIFO size prevents deadlock across clock domains.

Explore how a FIFO in FPGA enables streaming between modules, using blocking and non blocking writes and reads with full and empty signals.

Define a streaming interface using the api underscore five four for signaling between ports and fifo in hls. Connect data out and data in with the xls stream data type.

Explore a Vitis-HLS streaming example using a fifo to synchronize an up counter from 0 to 9 with a pulse generator in a multi-cycle design, via ap_five_four interface.

Configure and integrate the generated streaming FIFO IP in a Vivado project using the IP integrator, connect pulse generator and up counter, and program the board.

Explore the usage and memory mapping of arrays in high-level synthesis for FPGA, including top-function arguments, internal variables, NHS IP structures, and memory interfaces.

Understand how high-level synthesis maps arrays to FPGA memories, selecting block RAM, FIFO, or RAM via top function arguments and memory interfaces for external or internal memories.

Explore array issues before and after synthesis, including simulation memory limits and performance. Learn strategies to map arrays to rom or ram, use static qualifiers, and careful initialization.

Block RAM in Xilinx FPGAs stores data and supports various widths, depths, and single or dual-port modes, with memories configured via the Block Memory Generator IP.

Demonstrate writing to and reading from a dual-port BRAM via Vitis HLS using the AP memory interface, with data displayed on LEDs, and analyze latency.

Connect read and write IPs to a dual-port block memory in a Vivado project, configure the block memory generator for true dual-port RAM, and synchronize with pulse signals.

Explore how to use pointers in high-level synthesis for FPGA, defining them in design functions or as top-level arguments, and synthesizing into wire interfaces or handshaked protocols for streaming data.

Explore the basic concepts of pointers in hardware and software, including addresses, the asterisk as pointer, the ampersand for address, and using pointers to access memory, arrays, and seven-segment displays.

Learn native pointer casting in high-level synthesis using native C++ types. See how int and short int casting affect memory layout and outputs in top function with a test bench.

Understand how top-level pointers as function arguments are synthesized with proper interfaces for data access outside the xlsx IP, using wire, fifo, or handshake interface protocols.

Pointer arithmetic moves a pointer to the next memory location without changing the memory’s value, and for hardware synthesis replace top-function pointers with an array interface and AP memory interface.

This lecture explains pointer multi access on the interface and how multiple reads and writes can cause unexpected behavior, highlighting the XSS stream class and volatile indexing.

Explore memory mapped communication, memory map system, and exit protocol for FPGA IPs; learn master-slave roles, AXI interface, interconnects, and how to control LEDs and read switches.

Explore memory mapped interfaces in FPGA designs, detailing address space division, master-slave transactions, transfer cycles and burst transfers, with examples from Xilinx and 64-bit addressing.

Learn how the AXI protocol under AMBA enables memory-mapped communication with AXI4, AXI4-Lite, and AXI4-Stream, detailing five channels, bursts up to 256, and master-slave handshakes.

This lecture demonstrates building a memory-mapped IP design to drive 16 LEDs on the Basys 3 board with an AXI GPIO slave, including address mapping and bitstream generation.

Learn how master and slave addresses are structured, map slave domains into master address spaces, and assign base addresses and offsets for AXI access.

Design an AXI-based memory-mapped output IP that drives LEDs on a three-board FPGA by wiring a 32-bit register at address 0xA to LED data via a master AXI port.

Design a memory-mapped i/o block with two master ports to read switch status and illuminate leds, mapping slave ports into a shared master address space via offset addresses.

Develop an m-axi interface by using master access protocol to drive two x master ports for AC transactions between BRAM and IPs, with Vivado project setup, debugging, and LED output.

Learn loop optimization techniques and array restructuring to boost performance in high-level synthesis for FPGA. Explore unrolling, partially unrolled, merged and flattened techniques, and how to generate a given waveform.

Explore loop optimization techniques in high-level synthesis, including pipelining, unrolling, partially unrolling, merging, and flattening, to improve loop latency and throughput in matrix-vector multiplication and other compute-intensive routines.

Explore loop unrolling in high-level synthesis for FPGA, showing how unrolling by factors of two or four reduces loop latency and how array partitioning and BRAM ports influence performance.

Explore how loop pipelining overlaps iterations to boost throughput and reduce loop latency. See initiation interval, nested loops, and pipeline pragma shape unrolling and hardware performance.

Explore how data dependencies and the initiation interval limit loop pipelining in high-level synthesis, illustrated by a Mandelbrot loop that raises the initiation interval.

Learn to generate a waveform with a for loop in high-level synthesis, using rewind to overlap pipeline iterations and achieve initiation interval one.

Explore streaming data communication in FPGAs to reduce memory access overhead, enable real-time data management, and optimize compute-intensive applications using the XLS streaming library and producer consumer model.

Define and model streaming data using the producer–consumer paradigm, implement communication with FIFOs, and manage buffer depth to avoid deadlocks, highlighting HLS streams and potential throughput gains.

This lecture demonstrates synthesizing a top function argument into a fifo interface connected to an external fifo, with default api_fifo and optional axis interfaces.

Explore blocking and non-blocking stream operations in high-level synthesis for fpga, detailing deterministic blocking reads and writes versus non-blocking behavior, boolean status, and rtl/co-simulation and c-simulation considerations.

Explore data flow optimization for streaming applications by modeling tasks as a data flow graph, using FIFOs to enable parallel and pipelined execution while scheduling with production and consumption relations.