High-Level Synthesis for FPGA, Part 2 - Sequential Circuits

Build a simple lab to implement and examine high-level synthesis concepts for FPGA using a basis three evaluation board, a laptop, and the design toolset from the vendor site.

Learn how two main software tools translate C/C++ descriptions to HDL and package IPs, driving a Vivado-based flow from design capture to bitstream generation for FPGA programming.

Install vivado hlx by creating a xilinx account, downloading the unified installer for windows or linux, and using the wizard to install the design suite and three board definition files.

Test installation verifies the lab setup for sequential circuits, guiding you to create a project, select the target fpga board, synthesize, export hardware, and program the board via jtag.

Learn the fundamentals of sequential circuits, starting from a one-bit memory and flip-flops, and explore clock and reset signals, registers, and signaling in FPGA design.

Learn how the flip-flop serves as the basic memory cell in FPGA for sequential circuits, storing one bit by latching data on a clock edge.

Learn how sequential circuits use memory cells like flip-flops to store state, with a clock coordinating the interaction between the combinational logic and memory to produce outputs.

Explore how the clock signal governs sequential circuit performance with rising-edge sampling, set up time, and hold time, and show how propagation delay, clock period, and clock uncertainty shape margins.

States capture past inputs and outputs in flip-flops, defining a sequential circuit's behavior. Transitions between states, driven by clock edges, form a finite state machine.

Understand reset signals in sequential circuits: active high/low, asynchronous or synchronous, with flip-flop clears and options none, control, state, and all for memory cells.

Explore how registers—sets of flip-flops with a shared clock and reset—are described and synthesized from static variables, where size and structure depend on active bits and usage.

Describe a three-flip-flop shift register built with a multiple static variable in high-level synthesis, featuring clock and reset and a right-shift; ends with a four-bit left-shift quiz.

Introduce the single-cycle design technique for describing simple sequential circuits, using two examples to illustrate structure and design flaws, and analyze circuit signals for practical implementation.

Describe a simple sequential circuit with memory registers, driven by a clock, using a single cycle design and C/C++ static variables for registers, reads, logic, and writes.

Explore a single-cycle design to implement a parallel-to-serial converter, using a counter-based state machine to stream eight input bits from least to most significant, with start and end signals.

Design a serial-to-parallel converter with a single-cycle approach, capturing serial data into a multi-bit register and producing parallel output after the final bit, using start and end signals.

Integrate multiple IPs in Vivado to build sequential circuits with divide and conquer, single cycle per function, test and synthesize, then assemble in an IP-centric design flow.

explores building a test bench to validate a sequential circuit with the single cycle design concept, generating input waveforms and test vectors to verify functionality and timing through simulations.

Learn to implement and test a parallel-to-serial converter in a single-cycle FPGA design, using a test bench to drive inputs and observe eight-clock-cycle outputs.

Demonstrate serial-to-parallel conversion of eight-bit data driven by a start pulse and clock, observe the parallel output after eight cycles, and debug with a testbench and waveform viewer.

Generate input waveforms as test vectors for a clocked sequential circuit using a state register to produce single-cycle pulses. Lecture covers test benches, rtl simulation, timing at 100 mhz.

Explore the essential elements of a finite state machine—states, transitions, and registers—in a synchronous sequential circuit, where the clock drives state updates on the rising edge via conditional statements.

Describe an fsm using a C/C++ template with enum states, static registers, next-state variables, and a switch-case for transitions, illustrated by a five-state two three four six combination lock.

Explore high-level synthesis of a sequential combination lock for FPGA, handling enter pulses, X input validation, and seven-segment display outputs across five states with lock reset.

Demonstrates designing a combination lock on a fpga using Vivado, integrating a combination lock IP with a bouncer and a single-cycle pulse generator to clean push-button inputs.

Introduce a set of utility circuits to speed up high-level synthesis for fpga design, detailing timers, counters, pulse generators, clock generators, and edge detectors, with rtl simulation in Etchells.

Explore mechanical switch bouncing and design a debouncer using a clock-edge delay, a state machine, and a delay counter to output a clean pulse.

Design and simulate a synchronous up-counter counting pulses from zero to nine and driving a seven-segment display, using a two-state FSM for pulse detection with reset, enable, and direction.

Generate a slower clock from a fast clock using a clock division circuit, implementing a two-state generator with a 50% duty cycle and a 100 MHz to 5 MHz example.

Design a two-state machine that generates a single-cycle positive pulse on the rising edge of the input, using wait-for-one and wait-for-zero states with synthesis and simulation guidance.

Create a two-state counter-based state machine to generate a single-cycle, regular output pulse, keeping the output high for one input clock and low for the remaining cycles.

Detects rising and falling edges on an input with a simple sequential circuit, producing one-cycle pulses via a static previous input register and edge comparison, synthesized to a single cycle.

Explore how a finite state machine models sequential circuits, using a vending machine to illustrate design, debugging, and implementation of a digital controller for real applications.

Describe how a vending machine controller models behavior with a finite state machine, using nickel, dime, and quarter inputs to trigger dispense and change outputs.

Explore building a vending machine controller in Vivado, converting push-button inputs into single-cycle pulses via bouncer and pulse generator, with pulse detectors driving LEDs and bitstream generation.

Explore using the integrated logic analyzer IP and LRIP customizer to monitor runtime signals inside an FPGA, enabling real-time debugging of sequential circuits from high-level synthesis.

Explore debugging fpga designs at runtime using an integrated logic analyzer ip to monitor internal signals with probes, triggers, and sampling depth. Configure triggers and view captured waveforms for diagnosis.

Instantiate and monitor design signals in Vivado on the fpga board by adding a probe ip, configuring probes and trigger conditions, and generating the bitstream for runtime debugging.

Explore function pipelining in Etchells to optimize multi cycle hardware designs and boost performance. Define metrics for evaluating IRR filter pipeline designs and compare implementations.

Explore the concept of pipelining in sequential circuits, comparing sequential execution with micro-architectural stages, and define initiation interval and its role in maximizing throughput.

Explore function pipelining in multi-cycle designs by a two-cycle counter that drives a seven-segment display, compare single-cycle and pipelined approaches, and analyze timing and handshaking strategies.

apply the pipeline directive to the BCT counter to build a pipelined microarchitecture that accepts input each clock cycle, boosting throughput in high level synthesis.

Explore initiation interval, latency, and throughput for pipeline circuits, compare single cycle and pipelined designs, and explain how these metrics evaluate performance.

Demonstrate an iir filter example to illustrate pipeline performance metrics in high-level synthesis. Learn about feed forward and feedback coefficients, function design, and how initiation interval and latency affect throughput.