Hands-On ZYNQ: Mastering AXI4 Bus Protocol

Name: Hands-On ZYNQ: Mastering AXI4 Bus Protocol
Rating: 4.4 (210 reviews)

Create Verilog and C codes for implementing the AXI4 bus protocol on ZYNQ FPGA

Created byErwin Ouyang

Last updated 2/2025

English

What you'll learn

Use Xilinx AXI4-based IP Cores
Create your own AXI4-based IP Cores from scratch
Create an AXI4-based Hardware Accelerator IP Core (GCD case study)
Create an AXI4-based Transceiver IP Core (UART case study)

Course content

8 sections • 20 lectures • 3h 35m total length

Introduction9:48
This lecture is an introduction of the course.
Vivado Installation0:16
This lecture is about step-by-step how to install the Vivado.

Create the Hardware Design16:23
After completing this lecture, you will be able to:
Create a block design in Vivado.
Configure PS UART for using printf function.
Add AXI GPIO IP core as input and output.
Connect the AXI GPIO IP to LED and switch.
Generate bitstream file for the PL (FPGA).
Test the Hardware Design using XMD7:51
After completing this lecture, you will be able to:
Use XMD for downloading the bitstream into the PL and testing the hardware.
Write data to the AXI GPIO register that is connected to the LED.
Read data from AXI GPIO register that is connected to switch.
Create the C Program10:55
After completing this lecture, you will be able to:
Create a C code for reading the switches.
Create a C code for blinking the LEDs.
Send data from Zynq PS to PC via UART.
Add the Internal Logic Analyzer IP Core10:40
After completing this lecture, you will be able to:
Add an Internal Logic Analyzer (ILA) IP core to the synthesized hardware design.
Trigger the ILA using the XMD memory write (mwr) command.
Debug the Hardware Design5:51
After completing this lecture, you will be able to:
Trigger the ILA using the C program.
Trigger the ILA using the switch.

Simulate the Xilinx IP Core10:54
After completing this lecture, you will be able to:
Create a test bench file for simulating the Xilinx IP core.
Simulate the block design using Vivado simulator.
Create the Hardware Design9:02
After completing this lecture, you will be able to:
Use the AXI-Stream Data FIFO IP core.
Interface the AXI memory-mapped to the AXI stream using the AXI-Stream FIFO IP core.
Create the C Program11:55
After completing this lecture, you will be able to:
Create a C code for accessing the AXI-Stream Data FIFO.
Use the Xilinx library for programming the AXI-Stream FIFO.

Create the Shift Register in Verilog11:58
After completing this lecture, you will be able to:
Create a Verilog module of the shift register.
Create a test bench file for simulating the shift register.
Simulate the shift register using Vivado simulator.
Create the AXI4-Lite Interface in Verilog27:38
After completing this lecture, you will be able to:
Create a Verilog module of memory-mapped (AXI4-Lite) to custom (shift register) interface.
Create a test bench file for simulating the memory-mapped to custom interface.
Simulate the memory-mapped to custom interface in Vivado simulator.
Create the Hardware Design and C Program22:28
After completing this lecture, you will be able to:
Integrate the AXI4-Lite shift register to the Zynq PS.
Create a C code for accessing the AXI4-Lite shift register.

Create the AXI4-Stream Multiplier in Verilog14:01
After completing this lecture, you will be able to:
Create a Verilog module of the AXI4-Stream multiplier.
Create a test bench file for simulating the AXI4-Stream multiplier.
Simulate the AXI4-Stream multiplier using Vivado simulator.
Create the AXI4-Lite to AXI4-Stream Interface in Verilog9:14
After completing this lecture, you will be able to:
Create a Verilog module of the memory-mapped (AXI4-Lite) to stream (AXI4-Stream multiplier) interface.
Create a test bench file for simulating the memory-mapped to stream interface.
Simulate the memory-mapped to stream interface using Vivado simulator.
Create the AXI4-Stream to AXI4-Lite Interface in Verilog20:29
After completing this lecture, you will be able to:
Create a Verilog module of the stream (AXI4-Stream multiplier) to memory-mapped (AXI4-Lite) interface.
Create a test bench file for simulating the stream to memory-mapped interface.
Simulate the stream to memory-mapped interface using Vivado simulator.
Create the Hardware Design and C Program13:39
After completing this lecture, you will be able to:
Integrate the AXI4-Stream multiplier to the Zynq PS.
Create a C code for accessing the AXI4-Stream multiplier.

Requirements

Basics of Digital Systems
HDL (Verilog) and C/C++ programming experience
Vivado WebPACK (free) Edition 2016.04 (recommended) or higher
A ZYBO development board (or other ZYNQ boards)

Description

Note: Take this course if you want save money in training costs of similar contents. The Official Xilinx Traning Courses cost typically from 600 USD to 4000 USD. This course is not only teaches the Zynq Processing System (PS) but also the Programmable Logic (FPGA), and the interface between them.

Published (20 Apr 2019): The GCD accelerator and UART sections will be added later, and the course price will be increased, when those sections are added.

Update 1 (22 Apr 2019): English Subtitles/CCs are enabled for this course

Update 2 (02 Jan 2020): Add bonus lecture.

What is AXI?

Advanced eXtensible Interface (AXI) is an industry-standard, system bus for the connection between CPU and peripheral in System-on-Chip (SoC) design. Today AXI version 4 (AXI4) is used in many SoC that use ARM Cortex-A processors, such as Qualcomm Snapdragon, Samsung Exynos, Broadcom (used on Raspberry Pi), and many more.

What is ZYNQ?
ZYNQ is actually a SoC, not just a FPGA, because ZYNQ consists of hard processor system (ARM Cortex-A9) and programmable logic (Xilinx 7-series FPGA, equivalent to Artix-7 FPGA). The ZYNQ device enables the implementation of custom logic such as hardware accelerator in combination with software that runs on the ARM Cortex-A9. ZYNQ can also run Linux OS, which makes this device like the popular Raspberry Pi, but with FPGA inside.

This course is based on hands-on laboratory with a lot of examples. Sample codes are provided for every project in this courses.

You will receive a certificate of completion when finishing this course. There is also Udemy 30 Day Money Back Guarantee, if you are not satisfied with this course.

So, click the course button and see you inside the course.

Who this course is for:

Students or engineers who are working in Embedded or SoC design
Students or engineers who have a knowledge of HDL (Verilog) and C/C++ but new to AXI4 bus protocol
Students or engineers who are already using ZYNQ and want to create your own IP cores with AXI4 bus protocol

Hands-On ZYNQ: Mastering AXI4 Bus Protocol

What you'll learn

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Course content

Introduction2 lectures • 10min

===== Part I: Use Xilinx AXI4 IP Cores =====1 lecture • 1min

Chapter1: AXI4-Lite GPIO5 lectures • 52min

Chapter 2: AXI4-Stream Data FIFO3 lectures • 32min

===== Part II: Create AXI4 IP Cores from Scratch =====1 lecture • 1min

Chapter 3: AXI4-Lite Shift Register3 lectures • 1hr 2min

Chapter 4: AXI4-Stream Multiplier4 lectures • 57min

Bonus: Are you interested in learning AI Accelerator like Google TPU?1 lecture • 1min

Requirements

Description

Who this course is for: