Fundamentals of Verification and System Verilog

Learn how to build a verification bench around a design in SystemVerilog, apply inputs and stimulus, collect outputs, and compare with expectations to validate functionality.

Apply stimulus to the design under test and capture responses with a testbench. Monitor and automatically compare actual results to the expected responses to assess correctness and coverage.

Explore two verification strategies—directed (inadequate) testing and constrained random testing—and learn to plan, constrain randomness, achieve functional coverage, and maintain reusable test benches.

Design layered testbenches for verification using agents, drivers, monitors, and scoreboards to generate and observe transactions. Build scenarios with functional coverage and randomization to validate designs.

Learn how verification languages boost productivity by automating stimulus, reporting, and coverage analysis, compare hardware verification languages with design languages, and examine programmable interfaces such as C++ for verification tasks.

Explore why SystemVerilog was created to address Verilog's modeling and verification gaps. Identify features like constrained randomization, functional coverage, assertions, and C/C++ DPI integration that boost productivity and maintainability.

Learn tool support for SystemVerilog, including browser-based playgrounds, simulators, and test benches, with guidance on selecting vendors like Synopsys, Cadence, and Mentor Graphics.

Design a one-bit full adder in SystemVerilog with inputs A, B, C and outputs sum and carry, then illustrate multi-bit extension and test bench simulation.

Explore built-in functions and operators in SystemVerilog, including display and monitor, time, finish, and stop, and learn how arithmetic, logical, and relational operators drive verification tasks.

The logic type in SystemVerilog provides a four-state data type that replaces wire and reg, enabling faster simulation, reducing synthesis confusion, and supporting signed and unsigned variants.

Master fixed size arrays in SystemVerilog by declaring, initializing, indexing, and slicing arrays of specified length, with elements, indices, and vector operations demonstrated.

Explore packed and unpacked arrays in SystemVerilog, including how to declare, size, and access array elements, and manage bit-level storage and unused elements.

Explore dynamic arrays in SystemVerilog, learning how to declare, resize, and initialize arrays, manipulate their elements, and pass values to adapt memory size in verification tasks.

Explore how queues manage homogeneous data, supporting push front and back, pop operations, indexed insertions and deletions, and size checks, with bounded and unbounded examples.

Explore associative arrays in SystemVerilog for sparse memory modeling using non traditional indices, including strings. Learn key operations like for each, size, exists, first, last, next, prev, and delete.

Learn core SystemVerilog array methods, covering reduction meters, locator meters, and ordering meters, with hands-on examples of min, max, unique, find, sort, and shuffle, including arrays of objects.

The lecture weighs when to use fixed, dynamic, queues, and associative memory structures based on size knowledge, data sparsity, and access patterns, emphasizing memory efficiency and access-time trade-offs.

Explore user defined data types in systemverilog, including typedefs, structures (packed and unpacked), unions, and enums, with practical examples of initialization, assignment, and reuse.

Explore SystemVerilog packages that centralize data types, typedefs, enums, and structs to avoid include duplication. Learn to declare, import, and access package members with the scope resolution operator.

Explore type conversion and type casting in SystemVerilog, and understand assignment semantics, left-to-right versus right-to-left evaluation, and handling of vector and signed data.

Explore enumerations in SystemVerilog, define typedefs for enumerated types, assign default and custom values, use base types, and convert between enum and integers in test bench and state machines.

Learn string manipulation in SystemVerilog, using operators, concatenation, and substring, with length, indexing, and conversions to decimal, octal, binary, and lowercase.

Learn how SystemVerilog handles simulation time with time scale, time units, and time precision, including printing and formatting time in nanoseconds and picoseconds.

Compare continuous and procedural assignments in SystemVerilog, learn how always and initial blocks model combinational and sequential logic, avoid unintended latches, and use let constructs and packages for text replacement.

Explore blocking and non-blocking assignments in Verilog, using = for blocking and <= for non-blocking to illustrate sequential versus parallel updates within clocked blocks.

Explore flow control in SystemVerilog, including if, case, for and while loops, unique and priority conditions, timing with clock edges, and control flow in initial, always, and final blocks.

Explore functions in SystemVerilog, learning how functions enable code reuse, declare return types, pass arguments by position, by name, or by reference, and manage automatic versus static storage.

Explore the differences between functions and tasks in SystemVerilog, including static vs automatic storage, by-reference and by-name arguments, and how default values and outputs work.

Explore how local data storage and variable initialization behave in SystemVerilog, revealing memory space allocation for tasks, race conditions, and the automatic storage solution.

Discover how SystemVerilog interfaces simplify connecting design and test benches by bundling bus signals into reusable blocks, replacing complex port mappings and boosting maintainability and reusability.

Explore how to create a SystemVerilog interface, including connectivity, synchronization, and functionality, and learn how interfaces connect top-level designs, benches, and RTL modules for reusable signal sharing.

Learn how to implement and verify protocol functions inside a SystemVerilog interface. Analyze synthesis behavior, advantages, and trade-offs of interfaces for reusable, consistent connections between modules.

Explore how clocking blocks enable timing and synchronization in Verilog testbenches, defining skew, sampling relative to the clock, and interface driven signals.

Explain how program blocks control test benches in SystemVerilog, applying blocking versus non-blocking assignments in the reactive region to avoid races, manage scope, and finalize with exit or finish.

Explore advanced interfaces and cross module reference in SystemVerilog, including virtual interfaces, mailbox IPC, and dynamic interface connections across top modules.