Fundamental of Static Timing Analysis (Part 1)

Name: Fundamental of Static Timing Analysis (Part 1)
Rating: 4.2 (133 reviews)

Timing details about RTL to GDS (Part 1)

Created byPuneet Mittal

Last updated 4/2019

English

English [Auto],

What you'll learn

Know all the Fundamentals of Static Timing Analysis
Different stages in ASIC Design where Timing Analysis is useful.
Timing Arc and Unateness
What are different type of Delay and How those are calculated ?
Liberty File (.Lib File) Syntax

Course content

3 sections • 25 lectures • 4h 59m total length

Overview of VLSI Design Flow (Part 1)9:51
Explore the fundamentals of static timing analysis and delay calculations within the VLSI design flow, from system specification through architectural and functional design to physical realization.
Overview of VLSI Design Flow (Part2) - VLSI Frontend Design Flow10:07
Explore the front end of the VLSI design flow, from architectural and behavioral descriptions to RTL (Verilog), then logic synthesis, netlist creation, and functional verification.
Overview of VLSI Design Flow (Part 3) - VLSI Backend Design Flow11:08
Explore the VLSI backend design flow from functional verification to partitioning, placement, and chip planning, emphasizing clocks, flip-flops, routing, and static timing analysis.
Importance of Timing from RTL to Logic Synthesis14:35
Explore how timing flows from rtl to logic synthesis, guiding partitioning into blocks and defining data-transfer constraints between blocks; understand timing constraints, netlists, and timing optimization during technology mapping.
Timing Optimization during Logic Synthesis11:18
Analyze timing during logic synthesis and optimize with mapping, remapping of cells, and buffer insertion to improve delays and support floor planning and timing analysis.
Overview of Floorplan Aware Synthesis9:13
Apply floorplan aware synthesis to connect macro placement, timing analysis, and physical constraints, using floor plan data to optimize placement, routing, and the design exchange format.
Overview of Timing Check in Physical Design Flow5:28
Expose the timing check in the physical design flow, from floor plan and placement to routing and sign-off, using clock through synthesis and iterative fixes to ensure chip readiness.
STA Tool and Flow at different Stages of Design4:54
Learn the STA tool flow at different design stages, from pre-layout to post-layout, and how tools provide sign-off timing reports with netlists, load models, and operating conditions.
What is Static Timing Analysis13:10
Learn the fundamentals of static timing analysis, including static vs dynamic timing, how to analyze circuit parts, evaluate timing constraints, identify violations, and apply fixes.
STA Tool - Input output Files8:28
Explore preparing input and output files for static timing analysis, including sdf and parasitic data, session saves, and merging spf files to generate timing reports.

Introduction to Timing Arcs10:19
Learn about timing arcs and delays between input and output in digital blocks, including rising and falling edges, to understand static and dynamic timing analysis and circuit behavior.
Net & Cell Timing Arc7:03
Understand static timing analysis concepts for nets and cells, including timing arcs, delays from input to output, and library models of buffers and inverters for rising and falling edges.
Timing Arc & Unateness of AND Gate9:49
Explore timing analysis for an and gate by examining timing arcs, rising and falling edges, propagation delays, and the unateness property under constant inputs using superposition.
Unateness of OR Gate and Improtance of Unateness5:30
Explore the unateness of the or gate and why maintaining positive unateness matters for timing analysis, showing how rising and falling edges affect input-output behavior.
Unateness of Logic gates6:16
The lecture explains the unateness of logic gates, classifying positive, negative, and non-unit behavior, and shows how rising or falling inputs affect outputs for buffers, inverters, and xor.
System Timing Arc and Unateness of Complex Gates7:28
Analyze system timing arc and unateness in complex gates by tracing how input pulses propagate through chains of buffers and inverters to predict overall timing behavior.
Sequential Cell Timing Arc5:07
Explore the sequential timing of flip-flops, focusing on set up and hold, clock-to-q, and recovery/removal timing. Learn about input-to-input and input-to-output timing arcs.
Library File Sample (.Lib File)1:23:58
Introduction about LIB FIle (LIB file and Timing Arc)7:33
Introduce lib file syntax and timing arcs, outlining pins, directions, and input–output relationships. Explain timing sections that specify delays, rise/fall transitions, and internal power and timing data.
Sequential Cell in Library File (.Lib File)9:40
Explore sequential cells in a library file, focusing on d flip-flops, clock relations, and set/reset behavior, with timing sections and timing sense guiding setup, hold, and recovery.

Introduction of Delay Concepts6:51
Explore delay concepts in static timing analysis, including net delay, input/output delay, and propagation and transition delays, and how they influence setup and hold violations.
Overview of RC Network13:12
Explore rc networks by examining the charging and discharging of a capacitor, the role of resistance, and the time constant, including 63 percent and five time constants.
Introduction of Propagation Delay8:27
Understand propagation delay in logic circuits, including dp alleged and dp actual, differentiate bp hl and dp lh, and learn how 50/50 input–output thresholds and dot live timing define tpa.
Calculation of Overall Propagation Delay10:01
Analyze how propagation delay is defined for inverters, distinguishing low-to-high and high-to-low paths (DP LH and DP HL), and compute the overall delay across back-to-back stages or buffers.
Introduction of Transition Delay9:54
Understand transition delay in static timing analysis, and distinguish it from propagation delay. Learn rising and falling transitions, 10–90 and 50% thresholds, and how delay numbers are defined.

Requirements

They should have heard Words Static Timing Analysis, Setup and Hold Time.
Should know the Truth table of D flip flop.
They should have some about ASIC flow

Description

Fundamental of Static Timing Analysis is going to cover almost all the details which you need to know to understand STA. In this course, you will learn

What are the things you should know to understand STA?

How tool do the calculation of a particular problem?

What's the meaning of Analyzing something and solving something?

Always remember - Tool is something which work based on user command - so it's very important to know what command we have to provide at what time. Which command - that's the something depends on Tools but what should be the approach is independent of Tool. In this course, Approach is main thing which you will understand.

Who this course is for:

This Course is meant for 2 type of Audiances. Students who need to understand Static Timing Analysis, and those who has some experience in this field. Basically anyone can take this cource who need to refresh their fundamentals or want to learn basic of STA

Fundamental of Static Timing Analysis (Part 1)

What you'll learn

Explore related topics

Course content

Introduction to Static Timing Analysis10 lectures • 1hr 38min

Timing Arc10 lectures • 2hr 33min

Delay5 lectures • 48min

Requirements

Description

Who this course is for: