Function Acceleration on FPGA with Vitis-Part 1: Fundamental

Explore how embedded systems evolve from on-premises computing to cloud and edge architectures, describing endpoints, edge devices, and IoT, and highlighting FPGA-based accelerators for edge applications.

Investigate the role of high level synthesis in end devices, edge platforms, and cloud computing, and how HLS enables pipelines and interfaces on FPGA based embedded systems.

Identify the hardware and software components, including the host computer and FPGA boards, and the design flow to create an accelerator with Xilinx tools and a final binary.

Set up a Linux workstation with Xilinx Vitus unified software platform, learn about software and hardware emulation, and generate FPGA bitstreams to test on zinc based FPGA boards or emulation.

Obtain and configure the Zcu 102 Vitis platform, build a hardware‑software platform, and prepare an SD card to boot the Zynq MP Linux system and run a Linux emulator.

Explain the structure of a Vitis project with three sub projects—kernel code, linking hardware modules, and host code—generating the bitstream and the ARM executable to boot a target Linux system.

Learn to write a host program for a hardware accelerator running on zinc, control a kernel, and explore the host-kernel relationship, OpenCL APIs, and Vitis concepts.

Write a host program in C++ for an OpenCL 1.2 FPGA accelerator, covering environment setup, device discovery, context creation, kernel argument configuration, and memory buffer management.

Explain burst data transfer between an FPGA kernel and memory, showing how contiguous data blocks are read and written with minimal latency and streaming throughput.

Define the host code for the scaling kernel, set buffers and arguments, and prepare input data. Migrate buffers, run the kernel, synchronize, and validate results against the golden model.

Create a vitus scaling project, implement kernel and host code, and run it through software emulation, hardware emulation, and hardware with sd card boot.

Develop an efficient image thresholding example using Vitis, optimizing kernel computation and data transactions, analyzing burst data protocols, and integrating an external software library with data files.

Explore binary thresholding as a simple image segmentation method, converting grayscale to binary with a 128 threshold on an fpga using Vitis.

Explain host code for an FPGA thresholding workflow using OpenCL and OpenCV, covering image read, grayscale conversion, buffer setup, kernel launch, and comparison with the golden model.

Demonstrates running an image thresholding example on the FPGA using Vitus, OpenCV, and hardware builds; transfer SD card files, connect via network, and debug with Vitus ID.

Develop and debug a linear relationship kernel for fpga acceleration by writing kernel and host code, compiling, and running in the software emulator.

Assign two memory ports to the kernel using pragmas to read A and B from DDR memory with separate bundles, boosting performance from 117.74 ms to 10.687 ms on hardware.

Discover how HLS optimizes loops to speed up kernels on FPGAs, using unrolling, pipelining, flattening, and merging, with memory considerations for on-chip and off-chip RAM.

This lecture defines iteration latency and loop latency, explains how loop trip count and latency directives influence performance, and shows how max or min latency constraints affect synthesis results.

Explore loop unrolling in HLS to accelerate FPGAs: compare rolled, partially unrolled, and fully unrolled loops, and learn how unroll directives affect multipliers, memory ports, and parallel data access.

Explore the array partitioning optimization, boosting throughput by splitting block RAM into multiple arrays using the partition directive (name, dimension, factor, type: block, cyclic, complete).

Merge consecutive loops into a single loop to reduce latency and improve logic optimization. Use the loop_underscore_merge pragma to guide merging within a scope, bound by side effects restrictions.

Explore data dependencies in pipelined loops, including loop carried dependencies that raise the initiation interval, and how dependencies inside and between iterations affect performance in FPGA acceleration with Vitis.

Explore memory dependencies in FPGA design with Vitis, showing how Eprom with two access ports can constrain parallel reads and how memory partitioning increases ports to reduce the initiation interval.