Function Acceleration on FPGA with Vitis-Part 1: Fundamental

Name: Function Acceleration on FPGA with Vitis-Part 1: Fundamental
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Embedded System Accelerators with Vitis and HLS

Created byMohammad Hosseinbady

Last updated 10/2021

English

What you'll learn

Understanding the basic concepts of FPGA-Based embedded systems
Understanding the Xilinx Zynq 7000 SoC and Zynq UltraScale+ MPSoC architectures
Accelerating functions in the Xilinx Vitis unified software platform
Using C/C++/OpenCL for accelerating compute-intensive algorithms on Zynq platforms
Running the accelerated applications on software and hardware emulators
Running the accelerated applications on actual FPGAs
Working with Zybo-Z7-20 and Ultra96V2 Zynq-based FPGA platforms
Implementing three exciting projects with Vitis

Course content

15 sections • 93 lectures • 9h 25m total length

Introduction6:01
Course Structure6:32

Introduction3:12
Definition7:34
Explore how embedded systems evolve from on-premises computing to cloud and edge architectures, describing endpoints, edge devices, and IoT, and highlighting FPGA-based accelerators for edge applications.
FPGA Role4:21
HLS Role4:33
Investigate the role of high level synthesis in end devices, edge platforms, and cloud computing, and how HLS enables pipelines and interfaces on FPGA based embedded systems.
Zynq5:16
Zynq MPSoC5:49
Exercises0:14
1- Assume a design that uses HP0 and HP1 in a Zynq UltraScale MPSoC to read data arrays simultaneously at the frequency of 200MHz. What would be the maximum memory bandwidth utilisation?
2- What is the upper bound of the memory utilisation for reading data from a DDR memory in Zynq 7000 at the frequency of 150MHz?
Quiz

Introduction2:35
Identify the hardware and software components, including the host computer and FPGA boards, and the design flow to create an accelerator with Xilinx tools and a final binary.
Definition5:42
Set up a Linux workstation with Xilinx Vitus unified software platform, learn about software and hardware emulation, and generate FPGA bitstreams to test on zinc based FPGA boards or emulation.
Design Flow4:28
Exercises0:02
Quiz

Introduction2:26
Develop an efficient image thresholding example using Vitis, optimizing kernel computation and data transactions, analyzing burst data protocols, and integrating an external software library with data files.
Definition3:02
Explore binary thresholding as a simple image segmentation method, converting grayscale to binary with a 128 threshold on an fpga using Vitis.
Kernel Code5:58
Host Code4:27
Emulation -- Lab13:31
Hardware -- Lab8:00
Demonstrates running an image thresholding example on the FPGA using Vitus, OpenCV, and hardware builds; transfer SD card files, connect via network, and debug with Vitus ID.
Exercises0:33

Introduction2:16
Definition5:20
Kernel Code5:49
Host3:30
Lab -- Emulator11:03
Develop and debug a linear relationship kernel for fpga acceleration by writing kernel and host code, compiling, and running in the software emulator.
Lab -- Hardware10:01
Assign two memory ports to the kernel using pragmas to read A and B from DDR memory with separate bundles, boosting performance from 117.74 ms to 10.687 ms on hardware.
Exercises0:11

Introduction3:26
Definition3:59
Loop Latency3:12
Loop Unrolling3:59
Array Partitioning5:08
Loop Merge3:46
Loop Pipeline3:54
Nested Loops: Flattening3:00
Data Dependencies2:25
Memory Dependencies2:50
Explore memory dependencies in FPGA design with Vitis, showing how Eprom with two access ports can constrain parallel reads and how memory partitioning increases ports to reduce the initiation interval.
Exercises0:52
Quizzes

Requirements

Understanding the basic concepts of C/C++ coding
Xilinx Vitis software unified platform
A Zynq-Based FPGA such as Zybo-Z7-20 or Ultra96v2

Description

This course is an introduction to function acceleration in high-level synthesis (HLS). The goals of the course are describing, debugging and implementing compute-intensive algorithms on FPGA-based embedded systems using C/C++ language without any help from HDLs (e.g., VHDL or Verilog).

The course introduces the Xilinx Zynq embedded systems and then explains how to use Xilinx toolsets to map applications on them.

It uses the Xilinx Vitis unified software platform to describe real examples and applications for embedded systems. The course follows the software and hardware emulation schemes as well as running the applications on the actual FPGAs.

Each section of the course uses several examples, quizzes and exercises to explain complex designing concepts easily and smoothly.

Along the course, you will work with several examples describing the HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches. In addition, the course utilises two exciting projects to put all the explained concepts together to design real circuits and hardware controllers.

This course is the first of a series of courses on function acceleration on Zynq-based embedded systems. Whereas this course focuses on fundamental concepts, the other courses will explain different optimisation techniques in Vitis.

Who this course is for:

Hardware engineers
Software engineers who are interested in FPGA
Lecturers, researchers, professors who want to use FPGA-based embedded systems in lectures, courses or research

Function Acceleration on FPGA with Vitis-Part 1: Fundamental

What you'll learn

Explore related topics

Course content

Prologue2 lectures • 13min

Embedded Systems7 lectures • 31min

LAB Structure4 lectures • 13min

Hardware/Software Setup7 lectures • 1hr 4min

Vitis-DesignFlow7 lectures • 33min

Host Program6 lectures • 25min

Scaling Example9 lectures • 54min

Image Thresholding Example7 lectures • 38min

Linear Relationship Accelerator Example7 lectures • 38min

Loop Optimisation11 lectures • 37min

Requirements

Description

Who this course is for: