Function Acceleration on FPGA with Vitis-Part 1: Fundamental

Explore the role of FPGAs in a three-layer end device–edge–cloud computing framework, introducing zinc 7000 and zinc Ultrascale+ Mpsoc edge platforms and their accelerator design with AWS.

Explore how embedded systems evolve from on-premises computing to cloud and edge architectures, describing endpoints, edge devices, and IoT, and highlighting FPGA-based accelerators for edge applications.

Investigate the role of high level synthesis in end devices, edge platforms, and cloud computing, and how HLS enables pipelines and interfaces on FPGA based embedded systems.

Discover the Zynq 7000 structure: the processing system with two ARM Cortex-A9 cores and programmable logic with LUTs, BRAMs, DSPs, and I/O ports, connected to DDR memory via AMBA AXI.

Identify the hardware and software components, including the host computer and FPGA boards, and the design flow to create an accelerator with Xilinx tools and a final binary.

Set up a Linux workstation with Xilinx Vitus unified software platform, learn about software and hardware emulation, and generate FPGA bitstreams to test on zinc based FPGA boards or emulation.

Outline the four-part hardware software setup for FPGA accelerators: a powerful computer, Ubuntu Linux, Xilinx Vitus Unified Software Platform, and a zinc based embedded system.

Obtain and configure the Zcu 102 Vitis platform, build a hardware‑software platform, and prepare an SD card to boot the Zynq MP Linux system and run a Linux emulator.

Install the Ultra96 v2 Vitus platform for the board, then prepare an SD card with FAT32 boot and ext4 root partitions, and build and run vector addition on hardware.

test the zybo z7-20 with vitis by building and emulating a vector addition project, then prepare eight gigabyte fat32 sd card and run the vector addition app on embedded linux.

Understand the Vitis project structure by creating a test accelerator, then compile and run it on software and hardware emulations as well as an actual FPGA.

Explain the structure of a Vitis project with three sub projects—kernel code, linking hardware modules, and host code—generating the bitstream and the ARM executable to boot a target Linux system.

Learn how to compile four projects for software emulation in Vitis, including the kernel, linker, host, and top projects, and run them in a Linux emulator.

Build the hardware target to generate the FPGA bitstream and embedded boot files, copy them to an SD card, boot the board, and run the vector addition test via serial.

Learn to write a host program for a hardware accelerator running on zinc, control a kernel, and explore the host-kernel relationship, OpenCL APIs, and Vitis concepts.

Explore how Opencl enables heterogeneous computing with host and kernels communicating through the zinc FPGA's DDR global memory, using Opencl APIs and the Xti bridge in a sequential execution model.

Understand how the host submits commands to a queue and how the OpenCL runtime orders kernels on devices in-order execution, with the platform, contexts, and memory objects.

Outline the three main parts of an OpenCL host program for Xilinx tools—environment setup, command execution, and post-processing—covering platforms, contexts, queues, programs, buffers, and releases.

Write a host program in C++ for an OpenCL 1.2 FPGA accelerator, covering environment setup, device discovery, context creation, kernel argument configuration, and memory buffer management.

Define the scaling operator that multiplies floating point inputs by alpha and adds beta to produce an output array, with two scalar parameters and memory-mapped data pointers.

Describe kernel code in Vitus, focusing on C kernel style, extern C linkage to avoid name mangling, and building a for loop that reads, computes, and writes via Axi channels.

Explain burst data transfer between an FPGA kernel and memory, showing how contiguous data blocks are read and written with minimal latency and streaming throughput.

Define the host code for the scaling kernel, set buffers and arguments, and prepare input data. Migrate buffers, run the kernel, synchronize, and validate results against the golden model.

Create a vitus scaling project, implement kernel and host code, and run it through software emulation, hardware emulation, and hardware with sd card boot.

Develop an efficient image thresholding example using Vitis, optimizing kernel computation and data transactions, analyzing burst data protocols, and integrating an external software library with data files.

Explore binary thresholding as a simple image segmentation method, converting grayscale to binary with a 128 threshold on an fpga using Vitis.

Explain host code for an FPGA thresholding workflow using OpenCL and OpenCV, covering image read, grayscale conversion, buffer setup, kernel launch, and comparison with the golden model.

Run and test the image thresholding example in emulators by creating a project for the Z. Q 102 platform and compare hardware output with the OpenCV golden model.

Demonstrates running an image thresholding example on the FPGA using Vitus, OpenCV, and hardware builds; transfer SD card files, connect via network, and debug with Vitus ID.

Write the host code after the accelerator kernel, using opencl error codes and the underscore check macro to validate API calls. Set up buffers and verify against the golden model.

Develop and debug a linear relationship kernel for fpga acceleration by writing kernel and host code, compiling, and running in the software emulator.

Assign two memory ports to the kernel using pragmas to read A and B from DDR memory with separate bundles, boosting performance from 117.74 ms to 10.687 ms on hardware.

Apply foundational optimization concepts in high-level synthesis to loop statements, focusing on unrolling, pipelining, array partitioning, and data and memory dependencies to improve loop latency.

Discover how HLS optimizes loops to speed up kernels on FPGAs, using unrolling, pipelining, flattening, and merging, with memory considerations for on-chip and off-chip RAM.

This lecture defines iteration latency and loop latency, explains how loop trip count and latency directives influence performance, and shows how max or min latency constraints affect synthesis results.

Explore loop unrolling in HLS to accelerate FPGAs: compare rolled, partially unrolled, and fully unrolled loops, and learn how unroll directives affect multipliers, memory ports, and parallel data access.

Explore the array partitioning optimization, boosting throughput by splitting block RAM into multiple arrays using the partition directive (name, dimension, factor, type: block, cyclic, complete).

Merge consecutive loops into a single loop to reduce latency and improve logic optimization. Use the loop_underscore_merge pragma to guide merging within a scope, bound by side effects restrictions.

Learn how loop pipelining on FPGA accelerates performance by overlapping iterations, reducing latency, and controlling initiation intervals with pragma pipeline and the UDF parameter.

Explore how loop pipelining affects nested loops, including inner-loop pipelining and outer-loop unrolling decisions, and how flattening two nested loops into one enables single-loop pipelining.

Explore data dependencies in pipelined loops, including loop carried dependencies that raise the initiation interval, and how dependencies inside and between iterations affect performance in FPGA acceleration with Vitis.

Explore memory dependencies in FPGA design with Vitis, showing how Eprom with two access ports can constrain parallel reads and how memory partitioning increases ports to reduce the initiation interval.