Learn VHDL and FPGA Development Hands On

Create a Vivado project with the new project wizard, set name and location, add VHDL design and constraints, select the correct FPGA part, then synthesize and generate the bitstream.

Download and install the vivado design suite from Xilinx, create or sign in to a Xilinx account, choose Windows installer, and run the setup to install webpack and SDK.

Explore how to implement various hardware communication protocols on an FPGA using VHDL, including RC servos via pulse width modulation, PS/2 keyboards and mice, infrared, and remote control devices.

Explore pulse width modulation (pwm) and duty cycle, showing how a single pulse modulates width to control a buzzer and an RC servo. See how pwm signals can represent analog outputs by averaging a digital signal to produce smooth voltage.

Simulate your pwm design in Vivado by placing pwm_vd in design sources and pwm_sym.vd in simulation sources, set runtime to 100 microseconds, and run a behavioral simulation.

Learn how pulse width modulation controls an rc servo motor by mapping duty cycle to shaft angle, using 50 hz pwm signals and an fpga-based pwm generator.

Learn how pulse width modulation controls buzzer volume by varying duty cycle at a resonant frequency. Higher duty cycles yield louder sounds, while 0% or 100% PWM yields silence.

Explore pulse width modulation waveforms in VHDL and FPGA development, comparing duty cycles at 50%, 25%, and 75%, and learn how to control a buzzer with pwm.

Demonstrate a pulse width modulation terminal on Basys 3 board, controlling seven-segment display, LEDs, buzzer, and servo via UART commands. Adjust buzzer duty and servo angle with simple commands.

Explore infrared communication basics—infrared light, IrDA, and the NEC protocol—and learn how receivers on an FPGA development board convert pulses into data to control devices via line-of-sight remotes.

Understand infrared data transmission with the NEC protocol using pulse distance encoding to send address and command, including extended NEC and 38 kHz carrier toggling.

Demonstrates infrared receiver operation on a basis three board, using a 38kHz carrier, showing address 04 and command 44 on a seven-segment display with LEDs indicating inverse values.

Celebrate completing the fpga turbo series communication protocols and apply your new skills to implement any form of communication on your fpga board. Explore more fpga turbo series courses.

Explore the PS/2 communication protocol, its legacy keyboard and mouse data flows, pinouts, and how a USB-to-PS/2 microcontroller interfaces devices with an FPGA in this course.

Understand the PS/2 protocol, including clock and data lines, controller and host roles, and reading data on the falling edge of the clock in keyboard and mouse communication.

Learn ps/2 mouse interfacing for an fpga by decoding three data packets per movement, the status, x, and y bytes, sampled on the falling clock edge.

Demonstrate a PS two mouse receiver on a basys three board, controlling a servo and a buzzer via left, right, and center mouse actions with visual feedback.

Demonstrates a PS/2 keyboard receiver on Basys 3 board, using R/L to move RC servo and U/D to adjust buzzer volume, with number keys displaying 0–9 on the seven-segment display.

The lecture demonstrates the PS/2 keyboard interface between a keyboard and an FPGA host, showing data read on the falling clock edge and 11-bit frame with scan codes, not ascii.

Explore how a universal asynchronous receiver transmitter enables serial communication via rx and tx lines, with baud rate, cross-connected tx to rx, and rs-232 to 3.3v fpga voltage contexts.

Determine which development boards work for this VHDL and FPGA course, including basis three and two, Ardie, and Altera, and align them with seven-segment displays and LEDs.

Explore how ascii translates letters and characters into ones and zeros for fpga and computers, using the ascii table to map letters, numbers, and control characters.

Explore the UART protocol, including start and stop bits, data bits, optional parity, baud rate timing, and little-endian transmission for FPGA and serial ports.

Discover UART transmission by encoding ASCII characters O and K into binary with start and stop bits. Form little-endian data packets and calculate bit time at 115200 baud.

Explore a UART transmitter design for FPGA, featuring a state machine, baud rate counters, edge detection, and a shift register to serialize data with start and stop bits.

Design a three-state transmitter state machine with init, load, and shift states that uses start trans and done shifting signals to control data loading and shifting on the transmit line.

Learn to create a UART transmitter Vivado project, add VHDL sources and a simulator file, copy sources into the project, and configure the XC7A35T basis three board for RTL testing.

Learn to simulate and verify a uart transmitter using behavioral simulation, inspect waveforms for tx sim and tx ready sim, verify ascii transmission of hello within 2048 microseconds.

Design a four-state uart receiver state machine that captures serial data from the rx line into a data register, signaling data valid signal when a byte arrives, for fpga implementation.

Create a UART receiver project in Vivado by setting up an RTL project and adding VHDL sources. Simulate the design to verify syntax and functionality, using copy sources for organization.

Set up vhdl uart receiver simulation, place r_uart.vhdl and r_uart_sim files in the correct directories, and run a 1200 us behavioral simulation to verify ascii outputs and led seven-seg data.

Explore the UART controller state machine from init to execute command, detailing signals, state transitions, and command handling for LED and seven segment outputs.

Create a Vivado Uart controller project by importing VHDL design files, adding a constraints file, and selecting Artix-7 family with the CPG-236 package for Basys 3, then simulate and verify.

Simulate the uart controller to verify operation, running a 15,000 microseconds test to confirm the transmit instruction state, wait for command and wait for argument states, and register values.