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Learn MoreFPGA Timings P2: Clock Domain Crossing(CDC) with Vivado 2024
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FPGA Timings P2: Clock Domain Crossing(CDC) with Vivado 2024
Step by Step Guide from Scratch
Created byKumar Khandagle
Last updated 7/2025
English
What you'll learn
- Metastability physics and its impact on clock-domain crossings.
- Distinction between Static Timing Analysis and CDC verification in Vivado 2024.
- Generation and interpretation of Vivado report_clock_interaction and report_cdc outputs.
- Design and insertion of two- and three-stage synchronizers with correct ASYNC_REG usage.
- Decision-tree methods for safe single-bit transfers, pulses, and reset crossings.
- Techniques for coherent multi-bit transfers using Gray counters and XPM_CDC primitives.
- Calculation and optimization of Mean Time Between Failure (MTBF) for reliable designs.
Explore related topics
Course content
5 sections • 133 lectures • 5h 8m total length
- What is CDC ?1:51
Learn how clock domain crossing enables safe data transfer between distinct clock domains in FPGA designs, and how metastability, data corruption, and glitches arise without proper synchronization.
- STA vs CDC0:37
- Understanding Metastability P13:13
Explore metastability in clock domain crossing, showing how unstable inputs near 0.4–0.8 V can miss setup time, forcing a flip-flop to settle unpredictably and affect the next clock domain.
- Understanding Metastability P22:42
Metastability occurs when a flip-flop captures a signal changing near a clock edge, leaving output undefined around 0.4 to 0.8 volt. Metastable values can cause synchronization failure in clock-domain crossing.
- Effects of Metastability2:41
Explore how metastability destabilizes signals when crossing clock domains and learn how meeting setup and hold times and proper CDC techniques prevent illegal outputs and glitches.
- Revisiting Metastability3:36
Explore metastability in clock-domain crossing by analyzing a dual flip-flop setup with cross-domain input, illustrating setup violations, unstable outputs, and the settling time that follows.
- Demonstration P11:30
Model two clock domains with an intermediate signal and two flip-flops to analyze clock-domain crossing. Synthesize the design to reveal CDC issues and validate behavior across domains.
- Demonstration P23:11
Learn to define two clock domains in Vivado, apply timing constraints for clocks a and b, and use report cdc to analyze clock-domain crossing.
- Design Code0:15
- Constraints0:13
- Sync vs Async domains0:36
- Clock Interaction report P13:10
Analyze the clock interaction report to study timing paths crossing clock domains, including setup and hold times, and metastability. It shows a source–destination matrix, with black indicating no path.
- Clock Interaction report P23:48
Learn how Vivado analyzes timing between clocks in clock domain crossing, from a single source to asynchronous clocks, using color cues to indicate constrained and ignored timing paths.
- Why STA (Static Timing Analysis) is performed only on synchronous clock domains0:23
- Clock Interaction report P33:27
understand how the clock interaction report in vivado uses color cues to indicate asynchronous clock domain crossing, metastability risk, and unsafe timing, and how set false path mitigates red warnings.
- False Violations4:51
Learn to interpret a clock interaction report in Vivado 2024 for clock domain crossing, covering slack, hold violations, and clock pair classifications.
- Understanding Setup & hold times P11:16
Define setup time as the minimum data stability before the clock edge and hold time as the minimum stability after the edge, illustrated with 1 ns and 0.5 ns examples.
- Understanding Setup & hold times P22:38
Explore how setup time uses worst-case delay to ensure data arrives before the clock edge and how hold time uses best-case delay to prevent changes after the edge.
- Clock Interaction report P42:57
Learn how to mark asynchronous clock domains with set clock groups and set false path in vivado, guiding the clock interaction report to ignore timing analysis between asynchronous paths.
- Use of Clock interaction report P12:23
Identify clock interactions across the design with a color-coded report to spot clock domain crossings, verify clock relationships (synchronous, asynchronous, or ignored), and prevent false violations before CDC analysis.
- Use of Clock interaction report P21:36
Identify signals crossing between clock domains using a clock interaction report, where colors indicate pass or no-pass, guiding you to fix missing constraints before proceeding with cdc flow.
- Usage of report_clock_interaction0:09
- report_cdc P13:27
Explore structural analysis of clock domain crossing using Vivado 2024 report CDC to identify safe versus unsafe CDC structures, ensure proper clock constraints, and prevent metastability and data coherency issues.
- Usage of report cdc2:21
Explore how report cdc analyzes clock domain crossings, verifies proper synchronizers, and how false path or clock group exceptions affect the analysis.
- Safe & Unsafe terminology2:33
Learn safe and unsafe CDC terminology in Vivado, implement two flipflop synchronizers on a single-bit or multi-bit transfer to prevent metastability, and verify paths with clock-pair constraints and CDC report.
- Understanding report_cdc P11:31
Learn the four report_cdc flavors in vivado, printing a summary of clock pairs and safety via TCL, and use detail mode to identify CDC structures with a unique number.
- Understanding report_cdc P23:23
Apply report_cdc to analyze clock pair crossings with asynchronous clocks, highlighting that missing a synchronizer yields unsafe data transfer, classified as critical, while unknown status requires deeper CDC structure analysis.
- Understanding report_cdc P34:10
This lecture demonstrates using report_cdc in Vivado to generate summary and detailed CDC reports for each path, identify unknown CDC circuitry, and verify the presence of synchronizers between clock domains.
- Understanding report_cdc info P13:25
Analyze vivado's report cdc to interpret severity levels from info to critical and understand cdc type, clock domain relationships, and absence of synchronizers for safe crossing.
- Understanding report_cdc info P22:46
Understand how report_cdc info analyzes clock domain crossing, detailing clock group exceptions (synchronous, asynchronous, exclusive) and constraints like false path and max delay, plus endpoints and status (safe, unsafe, unknown).
- Understanding report_cdc info P33:28
Analyze how Vivado reports report_cdc statuses across clock domains, distinguishing safe, unsafe, and unknown endpoints, and learn which topologies—combinational logic, fanout, multiple domains, and non-flip-flop primitives—trigger unsafe CDC.
- Understanding report_cdc info P44:19
Learn how report_cdc info flags unsafe or unknown clock domain crossings in Vivado 2024 and why safe CDC structures or two-flip-flop synchronizers address metastability between source and destination clocks.
- Usage of report_cdc0:09
- Interview Prep0:41
- Why combinational output should not be used as input to synchronizer P15:21
Explain how a combinational path to a synchronizer risks metastability in clock domain crossing. Use a register after the combinational logic to stabilize signals and improve MTBF.
- Why combinational output should not be used as input to synchronizer P24:19
Learn why combinational logic before a clock-domain crossing synchronizer is unsafe, and register that logic in the source clock domain to drive a two-flip-flop synchronizer for safe CDC.
- Why combinational output should not be used as input to synchronizer P31:48
Run a CDC check with report CDC in Vivado 2024, interpret warnings about a combinational output synchronized through a register, and ensure a known CDC structure is invoked for safety.
- Design Code0:24
- Constraints0:15
- Revisiting bad circuit2:45
Explore clock domain crossing with Vivado 2024, identify unsafe single-register transfers between asynchronous domains, and implement synchronizers to safely transfer data while inspecting report CDC for metastability risks.
- Synchronizer5:38
Learn how a two-flip-flop synchronizer safely transfers signals across clock domains in CDC designs. Mitigate metastability and ensure a stable, clean output for Vivado projects.
- Adding Synchronizer to design P12:13
- Adding Synchronizer to design P21:56
Add a synchronizer for clock domain crossing and use the rec async reg true attribute in Vivado 2024 to place cdc flip-flops together, improving mean time between failures.
- Design Code0:24
- Constraints0:15
- Usage of ASYNC_REG attributes P14:00
Use the async_reg attribute on synchronizers for clock-domain crossing in vivado 2024, placing two closest flip-flops to reduce metastability and improve mtbf, while validating with implementation results.
- Usage of ASYNC_REG attributes P22:51
Explore how async_reg attributes improve safe clock-domain crossing in vivado by using synchronized flip-flops, reducing CDC risk, and leveraging vivado CDC primitives and decision tree for different data transfer scenarios.
- Design Code0:24
- Constraints0:26
- Recommended Practices for CDC Flops P1 : Low Fanout2:07
Adopt two techniques to reduce CDC flip-flop load: keep the synchronizing stage with low fanout on two flip-flops and place a buffer after the stage with a resistor.
- Recommended Practices for CDC Flops P2 : Minimize delay0:50
Minimize CDC delay in Vivado by applying async reg attributes to both registers, ensuring the closest flip-flops are used, with minimal load to improve MTBF.
- CDC flow P13:01
Explore the cdc flow in Vivado 2024, using two-flip-flop synchronizers and built-in primitives to transfer single-bit and multi-bit data across clock domains while covering synthesis and report clock interaction.
- CDC flow P22:52
Analyze clock domain crossing by evaluating the CDC report and clock constraints, iterating RTL synthesis and synchronizer design between two clock domains until data transfers safely between domains.
- Using Primitives in CDC flow P13:10
Explore using Xilinx primitives in cdc flow with Vivado 2024 to safely transfer single-bit data between clock domains using an Xpm cdc primitive.
- Using Primitives in CDC flow P23:09
Use primitives in the CDC flow P2 with Vivado 2024 to run report clock interaction, generate a CDC report, and verify synchronizers between asynchronous clock domains.
- Using Primitives in CDC flow P32:56
Analyze and implement clock domain crossing in Vivado using synchronizers, verify timing constraints, and apply single-bit primitives to safely transfer signals across clock domains, then extend to multi-bit primitives.
- Design Code0:22
- Constraints0:13
- Interview Prep0:46
- ways to build Synchronizer P12:36
- ways to build Synchronizer P23:20
Leverage vendor CDC primitives to reliably mitigate metastability and simplify clock-domain crossing in Vivado 2024. For learning, manual synchronizers work, but production prefers vendor primitives for portability and ease.
- Single Bit Decision Tree2:38
- Async Reset P13:01
Learn how xpm cdc async reset transfers an asynchronous reset across clock domains, producing asynchronous assertion but synchronous deassertion in the destination domain via a two-flip-flop synchronizer.
- Async Reset P22:39
- Async Reset P34:13
Explore how to synchronize an asynchronous reset to a 100 MHz destination clock using a four-stage flip-flop CDC primitive for safe GPIO write and read operations.
- Code0:36
- Sync Reset P13:30
Learn how CDC sync reset safely transfers a synchronous reset between clock domains using multi-stage synchronizers, init values, and sim assertion checks in Vivado 2024.
- Sync Reset P22:33
Demonstrates a sync reset using a PLL to generate 108 MHz and 54 MHz from a 27 MHz input, with two clock outputs and lock-based reset release.
- Sync Reset P33:25
Implement a sync reset in clock domain crossing using Xpm CDC with Vivado 2024. Initialize reset values, wait for MCM and PLL lock, and deassert across two-frequency and four-frequency domains.
- Code1:35
- Understanding xpm_cdc_single4:53
Explain how xpm_cdc_single safely transfers a single-bit signal across clock domains with a flip-flop chain to mitigate metastability, plus options for an optional source register and destination flip-flop count.
- xpm_cdc_single used case P14:14
Learn clock domain crossing using xpm cdc single to transfer the pixel clock from a 25–48 mhz domain into a 200 mhz system clock in an hdmi or vga controller.
- xpm_cdc_single used case P24:59
Explore xpm_cdc_single for clock-domain crossing of a noisy switch with 15 ms debouncing. Synchronize in the destination clock using a three-stage flip-flop and a debouncing counter.
- Code1:15
- Understanding xpm_cdc_pulse P12:52
Understand how the xpm_cdc_pulse clock-domain crossing primitive synchronizes a brief pulse from a source to a destination clock domain, with programmable synchronizer stages, optional resets, and simulation checks.
- Understanding xpm_cdc_pulse P22:20
Explain how to configure xpm_cdc_pulse for clock domain crossing with Vivado 2024, including destination and source resets, synchronizer flip-flops, and timing calculations to ensure valid pulses.
- Understanding xpm_cdc_pulse P31:30
use xpm_cdc_pulse p3 to enforce a minimum gap between source pulses equal to twice the maximum of source and destination clock periods, and maintain reset duration when resets are enabled.
- Understanding xpm_cdc_pulse P40:59
Understand how xpm_cdc_pulse enables safe pulse transfer for e-ink refresh across clock domains, from the onboard controller FSM clock to the epdi clock domain, using a synchronizer.
- Understanding xpm_cdc_pulse P52:19
- Code2:28
- Self Check Exercise 10:30
- Self Check Exercise 20:34
- Self Check Exercise 30:36
- Self Check Exercise 40:34
- Interview Prep0:33
- Why single bit CDC cannot be used for Multibits3:52
Show why single-bit cdc fails for multi-bit signals across clock domains due to skew, and introduce dedicated multi-bit cdc techniques guided by data type.
- Multi-bit Decision Tree P13:25
- Multi-bit Decision Tree P22:45
Explore Xpm primitives for clock-domain crossing: fifo async for streams, CDC handshake for guaranteed delivery, CDC array single for slow-changing data, and CDC grey for counters.
- Understanding XPM_CDC_ARRAY_SINGLE P13:35
Understand xpm cdc array single, a single-bit synchronizer used in multiple instances to safely transfer data across clock domains for slow-changing configuration, status, and interrupt information.
- Understanding XPM_CDC_ARRAY_SINGLE P24:01
Explore the Xfpm CDC array single primitive template, detailing required parameters, input synchronization, and per-bit signal transfer for flags and slow-changing config across clock domains coherence.
- Understanding XPM_CDC_ARRAY_SINGLE P33:46
- Code0:53
- Data Incoherency2:56
Explore the data incoherency and loss of data coherence when a single cdc primitive transfers a two-bit signal across clock domains, causing metastability and potential data corruption.
- Advantages of Gray over binary counters1:18
Learn how gray code minimizes bit changes to reduce metastability and data incoherency in clock domain crossing, using xpm cdc gray to transfer counter-like patterns between domains.
- Binary vs Gray Counters2:42
Compare binary and gray counters for clock domain crossing. See how gray counters reduce sampling errors when transferring multi-bit pointers between asynchronous clock domains.
- Counter Crossing Manual Approach P11:44
The lecture explains why a binary counter is unsuitable for clock domain crossing and shows using a counter to achieve single-bit changes when transferring data between clock domains.
- Counter Crossing Manual Approach P22:44
Explore crossing a counter between clock domains using an async fifo, bringing the write and read pointers across domains and understanding pointer extension via zero extension of a GRE counter.
- Counter Crossing Manual Approach P32:53
Extend the counter width to four bits for a depth-eight fifo to remove empty/full ambiguity, using zero extension so empty and full states remain distinguishable.
- Counter Crossing Manual Approach P41:54
Declare a pointer with independent binary and grey registers and implement a two flop synchronizer to transfer data between the write clock domain and the read clock domain.
- Counter Crossing Manual Approach P53:35
Implement a binary-to-gray converter to cross write and read pointers in a fifo, synchronizing the gray pointer across clock domains with two flip-flops.
- Counter Crossing Manual Approach P60:56
Handle reset and empty conditions when reading from a fifo, updating the read pointer and safely transferring it by binary to grey conversion across clock domains.
- Counter Crossing Manual Approach P74:57
Convert counter values from binary to gray and synchronize them across clock domains to safely predict fifo empty and full using gray comparisons.
- Code1:16
- Understanding XPM_CDC_GRAY P12:47
Explore clock domain crossing with xpm cdc grey to safely transfer counter-like values across clock domains, preventing data corruption in asynchronous fifos and using grey-coded multibit values.
- Understanding XPM_CDC_GRAY P23:12
Master clock domain crossing with XPM CDC gray in Vivado 2024, covering the four-stage synchronizer, init flip-flop options, sim checks, and gray-code based safe counter transfer between domains.
- Simple example of primitive P12:39
Transfer a 32-bit counter value safely from the reference clock domain to the output clock domain using the CDC gray primitive with a four-stage flip-flop synchronization.
- Simple example of primitive P22:55
- Simple example of primitive P32:00
Learn how to safely transfer a counter value across clock domains using a four-flip-flop synchronizer and gray codes, by adjusting source clock frequency to reveal valid outputs in simulation.
- Code0:39
- Using CDC GRAY primitives in FIFO P13:02
Use xpm cdc gray primitives to transfer right and read pointers between clock domains in a fifo via gray coding. Extend pointer width and synchronize to determine empty flags.
- Using CDC GRAY primitives in FIFO P22:19
Master clock domain crossing with gray-coded pointers in a FIFO. Use the XPM SPM CDC primitive for safe pointer transfer, reset, and full and empty flag generation in Vivado 2024.
- Using CDC GRAY primitives in FIFO P32:28
Analyze clock domain crossing safety using cdc gray primitives in a fifo with Vivado 2024, verifying clock constraints and interpreting cdc reports as safe for cross-domain data transfer.
- Code1:02
- Used Case P12:48
Explore using an Xpm CDC gray to transfer a test counter between source and reference clock domains, detecting clock inactivity and asserting a test clock stopped signal.
- Used Case P22:00
Detects whether the source clock is active by comparing test count sync to previous value in destination clock domain, with a 100-cycle threshold and updating last counter and output flag.
- Code0:32
- Self Checking exercise0:31
- Understanding xpm_fifo_async P13:11
Explore the xpm_fifo_async primitive for implementing an asynchronous fifo as a memory buffer to transfer data between two clock domains, with proper initialization and no-access rules.
- Understanding xpm_fifo_async P24:16
Explore xpm_fifo_async behavior, including write/read clock sensitivity, full/empty checks, and reset sequencing. Learn how memory type, read latency, and first word fall through enable zero or standard latency operation.
- Understanding xpm_fifo_async P32:47
- Self Checking exercise1:40
- Self Checking exercise0:30
- Understanding XPM_CDC_HANDSHAKE P12:55
Explain XPM_CDC_HANDSHAKE for clock domain crossing, detailing internal vs external handshakes, full handshake with destination acknowledgment, and how to configure synchronizer stages and data transfer timing.
- Understanding XPM_CDC_HANDSHAKE P23:35
Explore xpm_cdc_handshake in Vivado 2024, detailing external versus internal handshakes, how source data is synchronized across clock domains, and how destination requests, acknowledgments, and source receipts conclude a transaction.
- Understanding XPM_CDC_HANDSHAKE P33:24
Explore how xpm_cdc_handshake uses synchronizing flip-flops for clock-domain crossing, syncing source to destination as destination request and back as source acknowledgement, with data held in a register and external handshake.
- Understanding XPM_CDC_HANDSHAKE P41:20
Explore clock domain crossing with xpm_cdc_handshake, detailing asynchronous source and destination clocks, data and request synchronization through multiple stages, and external handshake effects on acknowledgments to complete transactions.
- Understanding XPM_CDC_HANDSHAKE P53:13
Explore how to use the XPM CDC handshake to transfer 8-bit data across clock domains with a two-stage synchronizer, using trigger, in_req, and done signals.
- Self Checking exercise0:46
- Interview Prep0:59
- Understanding MTBF & Improving strategies P12:25
Understand mtbf, the mean time between failure, as a reliability measure for metastability in clock domain crossing. Increasing flip-flops in a synchronizer extends settling time and exponentially boosts mtbf.
- Understanding MTBF & Improving strategies P22:23
Explore clock domain crossing and metastability, focusing on settling time tau and how faster flip flops reduce tau in Vivado.
- Understanding MTBF & Improving strategies P33:42
Improve mtbf in clock domain crossing by using two- or three-flip-flop synchronizers, reducing data change frequency, and applying handshake logic with valid strobe and fast-recovery flip-flops.
- Interview Prep0:27
Requirements
- Fundamentals of Digital Electronics, Verilog, STA.
Description
This course teaches FPGA engineers how to recognize, analyze, and close clock-domain crossings in Vivado 2024. It begins by contrasting CDC analysis with conventional static timing analysis and by explaining the physics and practical consequences of metastability. Students learn why static timing checks cover only synchronous domains, how metastability propagates, and how to read Vivado’s clock-interaction reports that flag potential false or true violations. The curriculum then moves to hands-on design work, where participants write and debug RTL that purposefully contains unsafe crossings, observe real metastability through simulations, and systematically repair the design. The class introduces two- and three-stage synchronizers, shows why combinational outputs cannot feed them directly, and explains the correct use of the ASYNC_REG attribute, fanout limits, and delay minimization. Single-bit transfers are handled with a decision-tree method that covers level and pulse crossings as well as asynchronous and synchronous resets. Multi-bit transfers follow, demonstrating why a single-bit synchronizer is inadequate, how to maintain data coherency with Gray counters or Xilinx XPM_CDC_ARRAY_SINGLE primitives, and how to build reliable dual-clock FIFOs using XPM_CDC_GRAY. Throughout the course, students generate and interpret Vivado report_clock_interaction and report_cdc output, apply safe and unsafe terminology, and practice waiver management and sign-off procedures. Practical labs culminate in an automated CDC analysis flow that mates TCL scripts with design checkpoints for repeatable closure. Finally, the class quantifies mean time between failure, shows how to push MTBF beyond product life by adjusting synchronizer depth and clock frequency, and equips engineers to defend their CDC strategy during design reviews. By the end, attendees can identify every crossing in a design, select the proper synchronizer or primitive, verify that all paths are safe, and deliver hardware that meets reliability targets on first silicon or bitstream release.
Who this course is for:
- Anyone preparing for Front end RTL Design role.