
Explore FPGA and SoC development using Vivado for hardware design and Vitis for embedded software on Xilinx Zynq Ultrascale MPSoC, with Linux, cross-compilation, and driver development.
Learn to run Linux on Windows with VMware by installing Ubuntu 18.04, configure the virtual machine, and prepare for using Vivado and Vitess in a development environment.
Install Xilinx Vivado and Vitis on Ubuntu by downloading the 21.1 Linux installer from Xilinx archive, making it executable, and running the installer to select Vivado Design Suite and Vitis.
Learn how to manually set up a Vitis project on Windows and Linux, including workspace creation, selecting xa, generating BSPs, building a hello world bare-metal app, and deploying to FPGA.
Create a Vivado project, familiarize with the GUI, add IP cores, and test your design with Open Hardware Manager using JTAG on the Z710 Zynq board.
Add the zinc 7000 processing system, connect DDR and fixed IO, and insert GPIO for LEDs, switches, and buttons using block automation; regenerate layout and rename IP blocks for clarity.
Configure the zinc processing system by enabling uart1, gpio, ethernet, and interrupts, adjust uart baud and ddr settings, then create an hdl wrapper and run synthesis, implementation, and bitstream generation.
Export hardware with the bitstream to generate an exa file for the Vitis workflow, including a complete hardware implementation, design wrapper, and BSP files.
Enable interrupts at the IP level, configure PL-to-PS fabric interrupts, and concatenate three sources—button, LED, and switch—into a single interrupt for the Vitis flow.
Install the JTAG cable drivers from the cable drivers directory on your Ubuntu workstation after Vivado to ensure processors are visible and you can deploy executables.
Test hardware health by launching the Xilinx hardware server xsct after sourcing the Xilinx environment, then verify targets show an APU processor with two cores and active ARM cortex processors.
Set up a Vitis workspace for Zybo by running the script to create bsp files and a main application, configure debugging and FPGA initialization, and use UART output.
Install gtkterm and configure the uart over usb on zybo at 115200 baud, select the correct /dev/tty usb port, enable local echo, and test with vitess.
Review BSP and x parameters to enable hardware access via base addresses and device IDs, initialize GPIOs, and wire software to FPGA IP cores.
Implement a hello world using the standard io library and printf over uart1 on the Zybo board; build and deploy in Vitis to view output on the console.
Learn to use stdio with uart one to read a username via scanf and print a hello message with printf, all through a Zybo Vivado Vitis workflow.
Implement a counter in standard C using scanf and printf, looping in endless loop until the user enters q to exit, with a break to stop and deploy the project.
Implement a uart menu example in c that prints a menu, accepts selections via uart, processes commands with a switch-case, collects username input, and exits when chosen.
Implement string concatenation with printf and sprintf, calculate age from a birth year, and print a formatted message to uart in a Zybo Vivado Vitis environment.
Explore the C primitive data types, including unsigned and signed integers (8/16/32/64 bit), floating points, characters, booleans, strings, and the void type, with examples like uint8_t.
Implement the first gpio led toggle on the Zybo board by initializing the gpio driver, using the led device id, setting output, and adding delays to observe the toggle.
Deploys an application to the zinc port and demonstrates a blinking leds pattern by turning all discretes on, waiting one second, then turning them off.
Implement a four-led binary counter on the Zybo platform using GPIO, with device id, channel, and 4-bit output, wrapping from 15 to 0, deploying via Vivado.
Implement a button input on a Zybo fpga using XGpio, configuring device id and button channel as input; read and print the button state with a 500 ms delay.
Deploy the image on the zybo and test button inputs by initializing the pins as input, reading discrete values in a while loop, and printing results as buttons are pressed.
Develop a generic interrupt controller using xparameters, gpio, and a dedicated interrupt controller, wiring button interrupts from fabric to ps7 and preparing a button handler.
Configure the interrupt controller and gpio for the Zybo board, initialize main and interrupt setup, enable button and global interrupts, and loop awaiting a button press.
Implement a button interrupt handler and register it with the generic interrupt controller (GIC) on the Zybo platform, enabling button interrupts and testing via Vivado and Vitis.
Configure the gpio interrupt controller and attach a button interrupt handler, then observe button states as 1, 2, 4, and 8 with presses. Power cycling resolves a buggy state.
Read the button state and print it to the UART console, then write that state to the GPIO LED using discrete writes and initialize the LED as an output.
Connect four buttons to four leds by copying button states to led states and blinking the leds; implement and wire the interrupt controller and button handler to uart output.
In this course, you will learn the entire SoC (System-on-Chip) development process using the Zybo Z7-10 development board. We will cover hardware design with Vivado, embedded software development with Vitis, and FPGA programming through hands-on applications.
This course focuses on Xilinx’s Zynq-7000 SoC architecture, bringing together both FPGA and embedded processor-based development processes. First, we will create hardware components using Vivado, then write embedded C code for the ARM processor using Vitis. Finally, we will develop real-world applications by managing data flow between the FPGA and the processor.
Topics Covered in This Course:
Creating a hardware block diagram in Vivado
Data communication between FPGA and processor
Embedded software development with Vitis
Controlling fundamental components such as GPIO, UART, and Timers
Integration of FPGA and ARM processor
Debugging on real hardware and performance analysis
Zynq SoC architecture and memory management
Additional Features:
Access to all course codes via GitHub
Mini quizzes at the end of lessons to reinforce learning
This course is ideal for students, engineers, and enthusiasts who want to gain hands-on experience in FPGA and embedded systems. It is also suitable for beginners in FPGA or SoC development, as each topic is explained from scratch.
If you want to develop projects with the Zybo Z7-10 or learn how to use Xilinx tools, this course is perfect for you. By the end of the course, you will have a solid understanding of the SoC development process.