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Digital System Design with FPGA using Verilog
Rating: 3.5 out of 5(10 ratings)
115 students
Created byMaqsood Ali Mughal
Last updated 1/2023
English

What you'll learn

  • Learn Verilog from scratch on Vivado platform
  • Design finite state machines (FSM) with real world application such as games
  • Learn Verilog to establish an interface between Vivado and FPGA, and implement design onto FPGA
  • Create testbench files, simulate and analyze logic circuit diagrams to verify the logic

Course content

2 sections • 19 lectures • 8h 32m total length

  • FPGA for BEGINNERS➟How to Get Started with Basys 3 Board and Vivado?25:11

    A thorough introduction to Basys 3 board with Artix 7 chip on it from Digilent.


    Table of Contents:

    00:35   Flow Process

    01:21  Introduction to Basys 3 Board

    02:54  Creating a New Project

    05:58 Design Entry (Verilog in Vivavdo)

    07:42 Creating a Constraint File

    13:10  Behavioral Simulation, Creating a Test bench File

    22:29  Implementation

    23:07 Generate Bitstream File

    23:25 Downloading Bitstream File onto the Basys 3 Board

    24:21 Functionality


    #electronicswithprofmughal #basys3board #fpga

  • Creating a testbench file and simulating your logic design15:20

    Implement Automobile Display Mirror System on an FPGA board that takes four 8-bit data from four different sensors and displays the data at the output using the selector switches of the Multiplexer. Assume that the 8-bit output then goes to a display that knows how to convert the binary number to decimal. Ref: Digital Design by Frank Vahid (2011, pg 90)

  • Verilog Description of D Flip Flop and Vivado Simulation13:19

    Learn how to simulate and Implement D Flip Flop using Verilog Description in Vivado.

  • Verilog Description of JK Flip Flop and Vivado Simulation19:17

    The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level “1”. Learn how to simulate JK Flip Flop in Vivado using Verilog Description (Behavioral Model) and implement it on to the Basys 3 Board.

  • Verilog Description of T Flip Flop and Vivado Simulation13:48

    Learn how to simulate T Flip Flop in Vivado using Verilog Description (Behavioral Model).

  • Designing a Basic Calculator | Verilog | Step-by-Step Instructions27:12

    Learn how to create a calculator that can perform basic operations like addition, subtraction, multiplication, and division in Verilog using Vivado environment.

  • Design a Slow Clock on an FPGA Board? | Verilog | Step-by-Step Instructions10:17
  • Debouncing Pushbutton | Verilog | Step-by-Step Instructions23:07

    Pushbuttons often generate spurious open/close transitions when pressed, due to mechanical and physical issues: these transitions may be read as multiple presses in a very short time fooling the program. This example demonstrates how to debounce a pushbutton on an FPGA board to get a single output pulse and a stable signal.Without debouncing, pressing the button once may cause unpredictable results.

  • Binary to BCD Conversion | Basys 3 FPGA Board | Step-by-Step Instructions1:20:51

    Learn how to design a Binary to BCD converter and implement it on Basys 3 FPGA board.


    The objective of this session is to build complicated combinational logic circuits, such as the binary to BCD converter. This tutorial will also be a transition from combinational logic to sequential logic circuits, such as counters. We will also apply the techniques learned from digital electronics lecture series on multiplexers and decoders to implement 4-digit 7-segment LED display.

Requirements

  • No programming experience required. The course will start at a very basic level and slowly transitions to an intermiediate to advance level.

Description

Digital circuits are the foundation upon which the computers, cell phones, and calculators we use every day are built. This course explores these foundations using modern digital design techniques to design, implement and test digital circuits ranging in complexity from basic logic gates to state machines that perform useful functions like calculations, counting, timing, and a host of other applications. Students will learn modern design techniques using a hardware description language (HDL) such as Verilog to design, simulate and implement logic systems consisting of basic gates, adders, multiplexers, latches, and counters. The function and operation of programmable logic devices, such as field programmable gate arrays (FPGAs), will be described and discussed in terms of how an HDL logic design is mapped and implemented.

Learn about Verilog as a beginner. In this course, we will learn about the basics of Verilog and how we can use it in the Vivado environment to generate combinational and sequential designs. We'll design finite state machines with real-world applications such as vending machines, T20 Cricket Games, Counters, etc., and implement them onto an FPGA board. We'll learn about the basic understanding of generating slow clocks, shift registers, flip flops, and counters to design basic-intermediate-advance-level FPGA projects. In addition, we'll generate testbench files to validate the logic and analyze the functionality of the design. The course will cover an explanation of the code line by line that students can follow and replicate on their own board while they watch the video.

Access to project files, supporting material, and code is included in the course

Come and join the course and become an expert on Verilog and FPGAs.

Who this course is for:

  • Digital Electronics Students
  • FPGA beginners
  • Verilog VHDL beginners
  • Electrical Engineering Students
  • FPGA Learners
  • FPGA Projects

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