FPGA Design with MATLAB & Simulink
3.5 (89 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
498 students enrolled

FPGA Design with MATLAB & Simulink

FPGA Design approach with System Generator of MATLAB/Simulink & HDL Coder, Course introduced the Complete Design Flow
3.5 (89 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
498 students enrolled
Created by Digitronix Nepal
Last updated 5/2019
English [Auto-generated]
Current price: $90.99 Original price: $129.99 Discount: 30% off
5 hours left at this price!
30-Day Money-Back Guarantee
This course includes
  • 3 hours on-demand video
  • 1 article
  • 8 downloadable resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
Training 5 or more people?

Get your team access to 4,000+ top Udemy courses anytime, anywhere.

Try Udemy for Business
What you'll learn
  • FPGA Development with Matlab and Simulink Tool.
  • Creating Projects with System Generator and HDL coder
  • Implementing FIR and IIR Filter on FPGA from System Generator
  • Implementation of OFDM modulation on FPGA
  • Zynq FPGA Design with Matlab/Simulink (System Generator)
  • LMS filter design with HDL coder from Matlab
  • Basic Idea of Matlab and Simulink
  • FPGA Design Basics
  • Idea of FPGA Design with Xilinx ISE and VIVADO
  • Idea of Hardware Description Language

This Course will let you know about "How to Design FPGA based Signal Processing Projects on MATLAB/Simulink".

This course is on Designing FPGA based Signal Processing Projects with MATLAB/Simulink and FPGA Design Tool (Xilinx VIVADO/ISE), we are going to use Xilinx System Generator (interface between MATLAB/Simulink and VIVADO/ISE) and HDL Coder. From this two tools we can design our projects on traditional MATLAB/Sumilink design flow; using Blocks and integrating blocks in Simulink or using MATLAB codes and finally converting this two types of design in to HDL or into Bitstream so we can program FPGA from MATLAB/Simulink or VIVADO/ISE.

We have session on FIR,IIR, LMS Filter Design and OFDM Modulation algorithm implementation on FPGA.

MATLAB & Simulink are the best tools for Signal Processing Projects, while FPGA are best hardware platform for such type of Signal Processing Projects cause of it's flexibility and processing capabilities.

Who this course is for:
  • Engineering Enthusiast
  • Computer Science
  • FPGA Design Enthusiast
Course content
Expand all 16 lectures 02:52:36
+ Section_1 Installation of Matlab/Simulink and VIVADO/ISE
2 lectures 14:57

How to Download and Install MATLAB/Simulink and VIVADO or ISE. This lecture tells you about the version compatibility of MATLAB/Simulink and VIVADO or ISE.

Preview 09:58
+ Section_2 Introduction to HDL Coder and System Generator
2 lectures 26:05

This session introduces the Matlab/Simulink, System Generator, HDL Coder and HDL Verifier tools for FPGA Design. We also have some basic design flow and its features on this lecture.

Preview 07:27

This session much elaborate about the System Generator and different block available at System Generator for FPGA Design, System Generator based different design Flow.

Preview 18:38
+ Section_3 Project with System Generator
5 lectures 50:40

Overview on System Generator, Basic project design methodology with system generator. We have lab session on this Section which are

-Lab 31: Basic System Generator Design for FFT

-Lab 32: Creating JTAG Configuration for FPGA Board in System Generator

Section_3 Basic Project with System Generator Overview
Section 3 Lab 30 Basic Project with System Generator

This Lab is on basic FFT based design with System Generator. This lab session includes "How to include FFT block on System Generator, configure it, integrate other system generator blocks as gateways , wavescope on the design".

Lab 31 Basic FFT Design with System Generator

This Lab session is on How to create JTAG configuration for uploading/dumping Sys Gen based Design on Hardware Co-Simulation Method to FPGA. We have showed up the "Creating JTAG Configuration for the Previous Project targeting Spartan 3E FPGA ".

Lab 32 Creating Custom JTAG Configuration
(Optional) Section_3 Lab 32 Demo: JTAG Implementation on Spartan 3E from Sys Gen
+ Section_4 Advance Design with HDL Coder
2 lectures 31:20

An overview of HDL Coder, IP core, HDL coder configuration with ISE as well as VIVADO has been introduced here. We also have details of LMS IP core design steps on Simulink.

Section 4 Advance Design with HDL Coder Overview

This is the Lab session on HDL Coder, this lab session is on "Least Mean Square-LMS Filter Design with HDL Coder". The necessary resources (project sources) are already attached with this Video. You have to go through that sources and locate on Matlab/Simulink as workspace.

LMS Filter Design_Advance Design with HDL Coder
+ Section_5 Advanced Design with System Generator
3 lectures 42:04

This lab is on Designing FIR Filter for Audio Processing with System Generator. You can take any audio from your local drive and process as shown in this lab session.

Lab 51 FIR Filter Design

This Session is on Design, Simulation and Implementation of OFDM (Orthogonal Frequency Domain Multiplexing) on System Generator and Targeting Spartan 3E FPGA.

OFDM Transceiver Design and Simulation Part I Transmitter Section

This session is on designing remaining receiver section from the previous lab and simulating the OFDM system on System Generator.

OFDM Transceiver Design and Simulation Part II Receiver Section & Simulation
+ Section_6 Zynq Development with System Generator & VIVADO
1 lecture 07:04

Implementing the Zedboard XADC and Pmod DA2 [DAC] on System generator for the interfacing project!

ZedBoard XADC+ Pmod Interfacing and Implementation on System Generator