FPGA Design with High Level Synthesis Tool (VIVADO HLS)
2.9 (55 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
370 students enrolled

FPGA Design with High Level Synthesis Tool (VIVADO HLS)

Design, Simulate, Synthesize & Export IP with VIVADO HLS (High Level Synthesis) : An FPGA Design Approach with C/C++
2.9 (55 ratings)
Course Ratings are calculated from individual students’ ratings and a variety of other signals, like age of rating and reliability, to ensure that they reflect course quality fairly and accurately.
370 students enrolled
Created by Digitronix Nepal
Last updated 1/2020
English
English [Auto-generated]
Current price: $83.99 Original price: $129.99 Discount: 35% off
22 hours left at this price!
30-Day Money-Back Guarantee
This course includes
  • 3.5 hours on-demand video
  • 3 articles
  • 11 downloadable resources
  • Full lifetime access
  • Access on mobile and TV
  • Certificate of Completion
Training 5 or more people?

Get your team access to 4,000+ top Udemy courses anytime, anywhere.

Try Udemy for Business
What you'll learn
  • Image Processing with VIVADO HLS & FPGA: Utilizing Computer Vision & Image/Video Processing Libraries on HLS
  • Sobel Edge Detection IP design in HLS, integrate IP in VIVADO tool and implement it on Zynq FPGA
  • Designing complete image processing pipeline on VIVADO tool with HLS IP and testing design on Zynq FPGA
  • Creating C/C++ Project, Simulating, Synthesizing and Exporting it with High Level Synthesis (VIVADO HLS)
  • Design, Synthesize, Simulate: Counter, Matrix Multiplier, Frequency Modulator ,Numerically Controlled Oscillator and Exporting Design to VIVADO tool
  • Debugging and Optimizing HLS Project for Resource Utilization on Targeted ZedBoard FPGA
Requirements
  • Basic Idea of C, C++
  • Basic Idea of HDL (VHDL/Verilog)
  • Basics of FPGA Design Flow
Description

Learn from Basic HLS Design & C-Simulation to Design Computer Vision Application [Real Time Sobel Edge Detection]

High Level Synthesis is new approach on FPGA Design with C/C++ Language.This Course covers : Creating new project on HLS, Running C Simulation on HLS, Synthesizing the HLS Project's which converts C/C++ Source in to Verilog/VHDL and System C, Running C/RTL Co-simulation, Exporting HLS Design in to IP core Format  to VIVADO IP Integrator. We also have include session on "Sobel Edge IP design in HLS, exporting it to VIVADO tool and then implementing/testing it on Zybo FPGA".

After Completing this course you will be able to Design, Simulate,Synthesize and Implement/Export HLS projects. HLS includes large number of C/C++ Libraries for Computer Vision (OpenCV), Video/Image Processing and Mathematical Computations which is very much complex while implementing on HDL/RTL.

In this Lab you are going to do lab on Design, Simulation , Synthesis and Implementation (Export Design) of Counter, Matrix Multiplier, Frequency Modulator, Numerically Controlled Oscillator (NCO Design) in C++. You will also integrate the exported HLS project with Zynq Processing System at VIVADO IP Integrator and Synthesize, Implement the Project on VIVADO IPI.

Who this course is for:
  • Electrical and Electronic Engineering
  • FPGA Design Enthusiast
  • Computer Science
  • High Level Synthesis Enthusiast
  • Hardware Developer working on HDL & interested on HLS
Course content
Expand all 17 lectures 03:29:44
+ Section 2 Design , Simulation,Synthesizing and Implementing with VIVADO HLS
6 lectures 01:24:23
Section 2 Lab 21 Design of Matrix Multiplier on VIVADO HLS
19:54
Section 2 Lab 22 Frequency Modulator Design Overview
13:21
Section 2 Lab 22 Frequency Modulator Design Simulation and Synthesizing on HLS
15:01
Section 2 Lab 23 NCO Design Simulation and Synthesizing Overview
10:47
Section 2 Lab 23 NCO Lab on VIVADO HLS and IPI
19:28
+ Section 3 Sobel Edge Detection with VIVADO HLS
5 lectures 01:08:43

The Overview of Sobel Edge Algorithm and the HLS Video Library has been detailed in this session.

Section 3_0 Sobel Edge Detection Overview with HLS and OpenCV
17:29

This project is Complete Tutorial on "Sobel Vivado HLS Kernel using AXI full interface". We have presented the all set of steps on this tutorial for designing and implementing the Sobel HLS Kernel on ZedBoard FPGA.

[Optional] Real Time Project: Sobel Vivado HLS Kernel Implementation on ZedBoard
00:43

This session is Implementation of Sobel Edge Detection Algorithm on HLS (C Programming Language). We will do the C Simulation, C synthesis and export RTL of this Sobel Edge Detection Project.

Section 31: Sobel Edge Detection with VIVADO HLS Overview and Lab Session
19:55

The HLS IP of "Sobel Edge Detection" has been synthesized and exported. That exported HLS design is "IP", which is now imported to VIVADO IP integrator (vivado main program) where we integrate with other IP's provided by Xilinx and Digilent. Finally we will create a block design and we will implement the "Sobel Edge IP" project in Zybo FPGA.

Section 3_3 Exporting Sobel Edge from VIVADO HLS and Integrating with VIVADO IPs
28:06

Demonstration of Real Time Sobel Edge Detection Project on Zybo FPGA.

Preview 02:30
+ Section 4: Advance HLS Optimization Methods: FIR algorithm Optimization with HLS
1 lecture 13:34

This session is on how to use code level and pragma level of optimization on FIR (Finite Impulse Response) design in VIVADO HLS Tool. We have shown the different HLS optimization strategies with this lab!

FIR Design Optimization with VIVADO HLS Tool
13:34
+ Bonus Section
2 lectures 00:29

What Could be the Next to this course?

What Next?
00:26

See the User Guides and Reference Design details.

User Guides and Reference Design on HLS
00:03