FPGA Design with High Level Synthesis Tool (VIVADO HLS)
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Try Udemy for Business- Image Processing with VIVADO HLS & FPGA: Utilizing Computer Vision & Image/Video Processing Libraries on HLS
- Sobel Edge Detection IP design in HLS, integrate IP in VIVADO tool and implement it on Zynq FPGA
- Designing complete image processing pipeline on VIVADO tool with HLS IP and testing design on Zynq FPGA
- Creating C/C++ Project, Simulating, Synthesizing and Exporting it with High Level Synthesis (VIVADO HLS)
- Design, Synthesize, Simulate: Counter, Matrix Multiplier, Frequency Modulator ,Numerically Controlled Oscillator and Exporting Design to VIVADO tool
- Debugging and Optimizing HLS Project for Resource Utilization on Targeted ZedBoard FPGA
- Basic Idea of C, C++
- Basic Idea of HDL (VHDL/Verilog)
- Basics of FPGA Design Flow
Learn from Basic HLS Design & C-Simulation to Design Computer Vision Application [Real Time Sobel Edge Detection]
High Level Synthesis is new approach on FPGA Design with C/C++ Language.This Course covers : Creating new project on HLS, Running C Simulation on HLS, Synthesizing the HLS Project's which converts C/C++ Source in to Verilog/VHDL and System C, Running C/RTL Co-simulation, Exporting HLS Design in to IP core Format to VIVADO IP Integrator. We also have include session on "Sobel Edge IP design in HLS, exporting it to VIVADO tool and then implementing/testing it on Zybo FPGA".
After Completing this course you will be able to Design, Simulate,Synthesize and Implement/Export HLS projects. HLS includes large number of C/C++ Libraries for Computer Vision (OpenCV), Video/Image Processing and Mathematical Computations which is very much complex while implementing on HDL/RTL.
In this Lab you are going to do lab on Design, Simulation , Synthesis and Implementation (Export Design) of Counter, Matrix Multiplier, Frequency Modulator, Numerically Controlled Oscillator (NCO Design) in C++. You will also integrate the exported HLS project with Zynq Processing System at VIVADO IP Integrator and Synthesize, Implement the Project on VIVADO IPI.
- Electrical and Electronic Engineering
- FPGA Design Enthusiast
- Computer Science
- High Level Synthesis Enthusiast
- Hardware Developer working on HDL & interested on HLS
The HLS IP of "Sobel Edge Detection" has been synthesized and exported. That exported HLS design is "IP", which is now imported to VIVADO IP integrator (vivado main program) where we integrate with other IP's provided by Xilinx and Digilent. Finally we will create a block design and we will implement the "Sobel Edge IP" project in Zybo FPGA.
Demonstration of Real Time Sobel Edge Detection Project on Zybo FPGA.