FPGA Design with VIVADO HLS -High Level Synthesis
What you'll learn
- Vitis HLS Installation, OpenCV Setup and LAB session
- Image Processing with VIVADO HLS & FPGA: Utilizing Computer Vision & Image/Video Processing Libraries on HLS
- Sobel Edge Detection IP design in HLS, integrate IP in VIVADO tool and implement it on Zynq FPGA
- Designing complete image processing pipeline on VIVADO tool with HLS IP and testing design on Zynq FPGA
- Creating C/C++ Project, Simulating, Synthesizing and Exporting it with High Level Synthesis (VIVADO HLS)
- Design, Synthesize, Simulate: Counter, Matrix Multiplier, Frequency Modulator ,Numerically Controlled Oscillator and Exporting Design to VIVADO tool
- Debugging and Optimizing HLS Project for Resource Utilization on Targeted ZedBoard FPGA
Requirements
- Basic Idea of C, C++
- Basic Idea of HDL (VHDL/Verilog)
- Basics of FPGA Design Flow
Description
At the ending of this course, we also have included how to "install Vitis HLS, setup OpenCV in Vitis HLS and performing the Vitis Vision 2020.2 based examples".
Learn from Basic HLS Design & C-Simulation to Design Computer Vision Application [Real Time Sobel Edge Detection]
High Level Synthesis is new approach on FPGA Design with C/C++ Language.This Course covers : Creating new project on HLS, Running C Simulation on HLS, Synthesizing the HLS Project's which converts C/C++ Source in to Verilog/VHDL and System C, Running C/RTL Co-simulation, Exporting HLS Design in to IP core Format to VIVADO IP Integrator. We also have include session on "Sobel Edge IP design in HLS, exporting it to VIVADO tool and then implementing/testing it on Zybo FPGA".
After Completing this course you will be able to Design, Simulate,Synthesize and Implement/Export HLS projects. HLS includes large number of C/C++ Libraries for Computer Vision (OpenCV), Video/Image Processing and Mathematical Computations which is very much complex while implementing on HDL/RTL.
In this Lab you are going to do lab on Design, Simulation , Synthesis and Implementation (Export Design) of Counter, Matrix Multiplier, Frequency Modulator, Numerically Controlled Oscillator (NCO Design) in C++. You will also integrate the exported HLS project with Zynq Processing System at VIVADO IP Integrator and Synthesize, Implement the Project on VIVADO IPI.
Who this course is for:
- Electrical and Electronic Engineering
- FPGA Design Enthusiast
- Computer Science
- High Level Synthesis Enthusiast
- Hardware Developer working on HDL & interested on HLS
Instructor
- 3.6 Instructor Rating
- 1,365 Reviews
- 15,903 Students
- 12 Courses
Digitronix Nepal is an FPGA Design Company serving global customers since 2013. As of the initiative of "Democratizing FPGA Education all over the World", Digitronix Nepal has partnered with LogicTronix [FPGA Design and Machine Learning Company] for creating online learning courses and tutorials on "FPGA, VHDL/Verilog, Computer Vision & Video Processing, High Level Synthesis (HLS), MATLAB/System Generator, Machine Learning Acceleratio, SDAccel, SDSoC, Pynq Development, etc."
Digitronix Nepal believes that with the "Ultra Low Cost and FREE Courses" on FPGA Design, enthusiast from any country can learn and explore on the Field of FPGA Design and grab the global opportunities on FPGA Design, ASIC/VLSI Design and Machine Learning Acceleration.