FPGA Design with VIVADO HLS -High Level Synthesis

Name: FPGA Design with VIVADO HLS -High Level Synthesis
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Design, Simulate, Synthesize & Export IP with VIVADO HLS : An FPGA Design Approach with C/C++

Created byDigitronix Nepal

Last updated 3/2023

English

What you'll learn

Vitis HLS Installation, OpenCV Setup and LAB session
Image Processing with VIVADO HLS & FPGA: Utilizing Computer Vision & Image/Video Processing Libraries on HLS
Sobel Edge Detection IP design in HLS, integrate IP in VIVADO tool and implement it on Zynq FPGA
Designing complete image processing pipeline on VIVADO tool with HLS IP and testing design on Zynq FPGA
Creating C/C++ Project, Simulating, Synthesizing and Exporting it with High Level Synthesis (VIVADO HLS)
Design, Synthesize, Simulate: Counter, Matrix Multiplier, Frequency Modulator ,Numerically Controlled Oscillator and Exporting Design to VIVADO tool
Debugging and Optimizing HLS Project for Resource Utilization on Targeted ZedBoard FPGA

Course content

6 sections • 19 lectures • 3h 46m total length

Overview of High Level Synthesis: VIVADO HLS19:53
How to Download, Install VIVADO & Get 30 Day Evaluation License6:12
Lab 1 Counter Design , Synthesizing and Exporting RTL on VIVADO HLS Tool16:28
HLS Optimization Methodology: Data type & Pragma Optimization11:10
In this session we will have detail on how to use the pragma directives for optimization of HLS implementation so that we can reduce the latency as well as resource utilization.

Lab 21 Matrix Multiplier Design and Simulation on HLS: Theoretical Overview5:52
Section 2 Lab 21 Design of Matrix Multiplier on VIVADO HLS19:54
Section 2 Lab 22 Frequency Modulator Design Overview13:21
Section 2 Lab 22 Frequency Modulator Design Simulation and Synthesizing on HLS15:01
Section 2 Lab 23 NCO Design Simulation and Synthesizing Overview10:47
Section 2 Lab 23 NCO Lab on VIVADO HLS and IPI19:28

Section 3_0 Sobel Edge Detection Overview with HLS and OpenCV17:29
The Overview of Sobel Edge Algorithm and the HLS Video Library has been detailed in this session.
[Optional] Real Time Project: Sobel Vivado HLS Kernel Implementation on ZedBoard0:43
This project is Complete Tutorial on "Sobel Vivado HLS Kernel using AXI full interface". We have presented the all set of steps on this tutorial for designing and implementing the Sobel HLS Kernel on ZedBoard FPGA.
Section 31: Sobel Edge Detection with VIVADO HLS Overview and Lab Session19:55
This session is Implementation of Sobel Edge Detection Algorithm on HLS (C Programming Language). We will do the C Simulation, C synthesis and export RTL of this Sobel Edge Detection Project.
Section 3_3 Exporting Sobel Edge from VIVADO HLS and Integrating with VIVADO IPs28:06
The HLS IP of "Sobel Edge Detection" has been synthesized and exported. That exported HLS design is "IP", which is now imported to VIVADO IP integrator (vivado main program) where we integrate with other IP's provided by Xilinx and Digilent. Finally we will create a block design and we will implement the "Sobel Edge IP" project in Zybo FPGA.
Sobel Project implementation on Zybo FPGA - Demo Session2:30
Demonstration of Real Time Sobel Edge Detection Project on Zybo FPGA.

Requirements

Basic Idea of C, C++
Basic Idea of HDL (VHDL/Verilog)
Basics of FPGA Design Flow

Description

At the ending of this course, we also have included how to "install Vitis HLS, setup OpenCV in Vitis HLS and performing the Vitis Vision 2020.2 based examples".

Learn from Basic HLS Design & C-Simulation to Design Computer Vision Application [Real Time Sobel Edge Detection]

High Level Synthesis is new approach on FPGA Design with C/C++ Language.This Course covers : Creating new project on HLS, Running C Simulation on HLS, Synthesizing the HLS Project's which converts C/C++ Source in to Verilog/VHDL and System C, Running C/RTL Co-simulation, Exporting HLS Design in to IP core Format to VIVADO IP Integrator. We also have include session on "Sobel Edge IP design in HLS, exporting it to VIVADO tool and then implementing/testing it on Zybo FPGA".

After Completing this course you will be able to Design, Simulate,Synthesize and Implement/Export HLS projects. HLS includes large number of C/C++ Libraries for Computer Vision (OpenCV), Video/Image Processing and Mathematical Computations which is very much complex while implementing on HDL/RTL.

In this Lab you are going to do lab on Design, Simulation , Synthesis and Implementation (Export Design) of Counter, Matrix Multiplier, Frequency Modulator, Numerically Controlled Oscillator (NCO Design) in C++. You will also integrate the exported HLS project with Zynq Processing System at VIVADO IP Integrator and Synthesize, Implement the Project on VIVADO IPI.

Who this course is for:

Electrical and Electronic Engineering
FPGA Design Enthusiast
Computer Science
High Level Synthesis Enthusiast
Hardware Developer working on HDL & interested on HLS

FPGA Design with VIVADO HLS -High Level Synthesis

What you'll learn

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Course content

Overview of VIVADO HLS4 lectures • 54min

Section 2 Design , Simulation,Synthesizing and Implementing with VIVADO HLS6 lectures • 1hr 24min

Section 3 Sobel Edge Detection with VIVADO HLS5 lectures • 1hr 9min

Section 4: Advance HLS Optimization Methods: FIR algorithm Optimization with HLS1 lecture • 14min

Section 5: Vitis HLS - OpenCV Installation and LAB Sessions1 lecture • 6min

Bonus Section2 lectures • 1min

Requirements

Description

Who this course is for: