Formal Verification: Exclusive Methodology 2022
What you'll learn
- Use Formal Verification effectively
- Describe issues that affect results from formal tools
- Use a systematic process for verification using formal methods
- Apply Property Checking in Formal Verification
- Have some knowledge of Formal Sign-off Methodology
- Apply Formal Sign-off to the correct design block
- Understand different formal verification use models of Formal Apps
- Basic knowledge of IC Digital Design and Verification
About this Course
Formal verification technology covers a very wide range, Methodology is the basis of this technology, and our course will mainly focus on formal verification methodology. Through the study and understanding of methodology, we can have a preliminary understanding of formal verification technology. This course can serve as a step for us to step into the field of formal verification and lay the indispensable foundation for later application of the technology in concrete practice.
This course answers many basic questions about the field of formal verification, explains the basic principles of the underlying technology of formal verification, proposes the latest formal signoff methodology, and expounds the technical development direction in the field of formal verification. By taking this course, you will have a certain understanding of formal verification techniques, as well as some basic knowledge of formal methodology. Let's first look at some of the basic goals of this course.
The use efficiency of formal verification has always been a big problem, and the correct method is essential. Regarding this issue, we will learn a lot about how to effectively use formal verification in this course.
The process of formal verification is highly dependent on the use of tools. Users need to have a certain understanding of the underlying technology of the tool in order to better utilize the advantages of formal verification. Here we can learn how to analyze and understand the verification results of the formal verification tool, and different responses will be taken for different results.
In order to use formal verification reasonably and effectively, it is often necessary to consider the entire verification process as a whole to play a role of formal verification. It is very necessary to apply formal methods to the verification process in a systematic process.
The goal of formal verification is in the form of property checking. The features of the design function are abstractly extracted one by one according to the description of the Spec, and these extracted features are translated and expressed through an property-based language. Then build a platform environment for property-based formal testing to compare with the functions in the design RTL code to verify the correctness of the design functions.
Formal verification, due to its fully proven nature, enables full functional verification of design modules and can be delivered as a final functional sign-off. A comprehensive Formal signoff methodology is provided in this course.
Formal verification pursues full proof, which has always been a considerable challenge for formal tools. At present, formal tools still have certain limitations in terms of computing power, which also makes the applicable design scope of formal verification not as arbitrary as simulation. Therefore, formal signoff requires appropriate design modules.
In addition to sign-off, there are many simple and easy-to-use formal applications of formal verification. These out-of-the-box applications provide corresponding formal solutions for different verification problems, which enable beginners or engineers without formal verification technical backgrounds to quickly and efficiently solve some problems encountered in verification.
Formal Verification Overview
In this chapter, we will introduce what formal verification is, its historical perspective, current trends, why it is needed, its requirements, its challenges, formal verification tool vendors, a comparison of the main vendors' tool features, and Formal capability levels.
Introduction to formal verification
In this chapter, we will introduce the formal verification framework, compiling a formal model, formal model concepts, checking assertions, assumptions, (Cone of Influence) COI, applying a proof algorithm, formal proof results, and formal proof performance, performance characteristics, formal tool setup and control, formal debug, formal engine access, formal verification and simulation comparison, differences between formal verification and simulation, ROI in formal verification, when to use formal verification, Formal property verification, formal verification applications.
In this chapter, we will cover property checking, property checking guidelines, end-to-end property checking, constraint development, formal signoff achieving, challenges and rewards of formal signoff, ROI and criteria of formal signoff, tracking of formal signoff, formal signoff flow, formal signoff testbench, formal signoff environment, the definition of complexity, measurement of complexity, definition of code and functional coverage, metrics types of coverage, controllability and observability of coverage, actions after coverage measurement.
Formal sign-off with Full Prove
In this chapter, we will introduce Formal Sign-off with Full Prove Flow, Environment Simplification, Assertion Simplification, functional split in the assertion simplification method, bit-width split in the assertion simplification, helper assertion, parameterization in the design reduction, partitioning in the design reduction, black-boxing in the design reduction, model abstraction, initial value abstraction, bound proof, over-constraint, and bug-hunting.
Formal Sign-off with Coverage
In this chapter, we will introduce Formal Sign-off with Coverage Flow, Formal Coverage, types of formal coverage, models of formal coverage, metrics of formal coverage, measurement of formal coverage, criteria of formal coverage, methodology of formal coverage, verification problems, signoff with coverage strategy, comparison of three verification flows including CDV, full-prove, and coverage.
Formal Verification Applications
As the out-of-the-box nature of formal verification applications is more and more accepted, it is becoming popular in the verification field. At present, the major formal verification tool suppliers are constantly launching their own formal verification applications. In this chapter, we will introduce some of the most used formal verification applications today.
Who this course is for:
- Formal Engineers
- RTL Design Engineers
- IP Designers
- Verification Engineers
- DV ManagersSystem Architects
- DV Managers
I am a master of microelectronics, and have about 15 years of experience in chip design, verification, and the EDA industry. As an expert in formal verification techniques, I have created a unique formal verification methodology. Many of the theories I have presented have been accepted as technical standards by most formal verification practitioners. I have many years of practical experience in formal verification and have developed and implemented formal verification solutions for many large-scale projects in many leading chip companies.