Embedded System Design with Xilinx Zynq SoC and Vitis IDE

Name: Embedded System Design with Xilinx Zynq SoC and Vitis IDE
Rating: 4.5 (180 reviews)

Using Xilinx Vivado Design Suite and Vitis 2020.2

Highest Rated

Created byKumar Khandagle

Last updated 9/2022

English

What you'll learn

Embedded System Design flow for Zynq AP SoC using Xilinx VITIS
Fundamentals strategies to use Xilinx Drivers
Development of C applications for Zynq Devices
Software Profiling with Vitis
Software and Hardware Debugging Strategies
Working with Interrupts

Course content

8 sections • 137 lectures • 10h 57m total length

Agenda1:16
Downloading Setup Files3:57
Sign into a Xilinx account and download the Vitis IDE for Zynq SoC, choosing between the self-destructing web installer or offline installer for a smooth setup.
Choosing Installation Settings2:28
LIC File
Adding License0:56
Digilent Board files: Download this before proceeding to the next Video
Adding Board files to Vivado1:51

Agenda1:49
Introduction P18:45
Navigate a three-pane design window to create a new Xilinx Zynq project, configure a block design with a processing system, and enable essential peripherals and constraints.
Introduction P23:50
Introduction P36:42
Export the hardware design as a platform after bitstream generation, then use Vitis IDE to create and build an application project and program the FPGA.
Fundamentals P1 : Project Types3:42
Fundamentals P2 : Flow Navigator8:18
Fundamentals P3 : When you need to add Hardware Constraints P15:01
Fundamentals P3 : When you need to add Hardware Constraints P23:45
Using TCL Script for Block Automation9:17
Important Files in Project Directory4:18
Reporting Mechanism P19:17
Reporting Mechanism P22:46
Demonstrate reporting mechanisms to the console in embedded design by comparing string, fixed point, and floating point outputs with format specifiers, and show build and debug steps in Vitis IDE.

Agenda2:22
Ways to access Peripherals from Zynq P14:02
Ways of accessing Peripherals from Zynq11:00
Fundamentals of XIL Drivers P14:14
Fundamentals of XIL Drivers P28:10
Fundamentals of XIL Drivers P33:36
Demonstration of XIL Driver Initialization3:57
Working with MIO LED P15:38
Working with MIO LED P216:15
Code0:14
Working with GPIO MIO LED and Pushbutton P14:16
Working with GPIO MIO LED and Pushbutton P25:16
Code0:16
Working with EMIO LED P15:31
Working with EMIO LED P211:44
Export hardware, build a Zynq platform, and configure EMIO GPIO pins to initialize and drive outputs, enabling blinking LEDs with proper tri-state handling.
Code0:23
Single Channel AXI GPIO P16:53
Single Channel AXI GPIO P211:48
Code0:13
Dual Channel AXI GPIO P12:56
Dual Channel AXI GPIO P27:18
Code0:16
Failed to update xparameters.h P11:32
Failed to update xparameters.h P27:44
Code0:06
Multiple Instance of AXI GPIO P14:24
Multiple Instance of AXI GPIO P28:12
Code0:16

Agenda1:27
Explore configuring the board and configuration model, selecting clock frequency, and managing intermediate complexity with multiple instances, modes, and verification for open hardware.
Overview5:19
Working with MIO UART P10:59
Working with MIO UART P2 : Changing Baud Rate Dynamically10:52
Code0:12
Working with MIO UART P3 : Sending Data6:50
Working with MIO UART P4 : Sending Data2:40
Code0:16
Working with MIO UART P5 : Receiving Data9:32
Code0:20
Working with UARTLITE P16:22
Working with UARTLITE P211:12
Code0:32

Agenda1:54
This agenda covers timer and counter blocks in zynq projects, including private timers, an independent triple timer counter, a 64-bit fabric timer, and timer ip dwell time in normal mode.
Overview3:15
Explore how processing system manages time with timers, including 32-bit and 64-bit timers and watchdogs, and learn to enable and use timer APIs in a Xilinx Zynq SoC with Vitis.
Working with Private Watchdog (WDT) Timer P14:09
Working with Private Watchdog (WDT) Timer P28:42
Working with Private Watchdog (WDT) Timer P38:36
Code0:19
Working with Private 32-bit SCU Timer P19:44
Working with Private 32-bit SCU Timer P27:35
Code0:19
Understanding AUTO-RELOAD Mode P17:12
Understanding AUTO-RELOAD Mode P211:55
Code0:23
Using RESTART_TIMER for AUTO RELOAD Mode3:09
Code0:23
Using Prescaler6:49
Code0:23
Working with TTC P14:05
Enable and configure triple timer counters in a Xilinx Zynq SoC design using Vitis IDE, customizing IP, setting clocks, and validating bitstream generation from a PCL script.
Working with TTC P226:40
Code0:28
Blinking effect on MIO LED with TTC P11:37
Blinking effect on MIO LED with TTC P210:51
Code0:37
Working with AXI Timer P14:14
Working with AXI Timer P216:49
Explore configuring the AXI timer in a Zynq design, cascade 32-bit timers to a 64-bit timer, initialize, set down-count mode, start, and poll for expiry.
Working with AXI Timer autoreload Mode P13:47
Working with AXI Timer autoreload Mode P24:16
Code0:19
Code0:27
Using Both Timers6:24
Code0:29
Using AXI Timebase WDT P14:05
Using AXI Timebase WDT P22:59
Code0:15

Agenda0:47
Working with Serial Terminal P11:51
Master debugging techniques with a serial terminal to verify initialization and observe variable values, using breakpoints and simple wrappers in Zynq workflows.
Working with Serial Terminal P23:19
Breakpoint P14:55
Breakpoint P24:10
Breakpoint P37:23
Explore debugging with multiple breakpoints, using step in, step over, and step return to inspect functions, variables, and control flow, while leveraging the variable view and breakpoint expressions.
Working with Memory Viewer P11:55
Working with Memory Viewer P22:55
Working with Memory Viewer P33:30
Working with XSCT P13:23
Working with XSCT P26:38
Working with Integrated Logic Analyzer P16:14
Configure clock, reset, and GPI IP to use integrated logic analyzer for debugging nets. Create a single system with multiple net slots and manage data depth to optimize FPGA memory.
Working with Integrated Logic Analyzer P28:11

Agenda1:21
Outline the application development pattern for Zynq systems, covering debugging and profiling, interrupt handling, driver fundamentals, and fabric APIs for GPO, timers, exact time, exchange rate, and CPU resources.
Fundamentals of Interrupt Drivers12:31
Working with GPIO Interrupts P14:46
Working with GPIO Interrupts P26:20
Working with GPIO Interrupts P39:11
Learn to initialize and handle gpio interrupts on Xilinx Zynq using Vitis IDE, including device lookup, config setup, enabling exception handling, and registering interrupt handlers with unique IDs.
Working with GPIO Interrupts P410:37
Code0:28
Multiple Interrupts P15:07
Multiple Interrupts P24:38
Multiple Interrupts P318:15
Initialize the gas driver and config, generate a gas config, and register and enable two independent GPIO interrupts (light switch and push button), with exception handling and console output.
Code0:35
Working with AXI Timer Interrupt P12:22
Working with AXI Timer Interrupt P211:09
Code0:26
Working with Private SCU Timer Interrupt P13:34
Working with Private SCU Timer Interrupt P212:50
Code0:28
Working with Private WDT Interrupt10:10
Learn to initialize and configure a private watchdog timer (WDT) in timer mode, enable interrupts and auto-reload, and verify initialization with device lookup, config structures, and driver APIs.
Code0:28
Working with TTC Interrupt P11:35
Enable the dc block within the processing system, configure the timer and clock settings, and validate that all data connections are correctly wired to the pins before generating the design.
Working with TTC Interrupt P29:51
Code0:32

Requirements

Understanding of Digital Electronics
Fundamentals of Computer Architecture
Fundamentals of C

Description

Xilinx Zynq SoC's are know to provide maximum performance per watt along with maximum reconfiguration flexibility. Zynq family features Dual-Core ARM Cortex A9 processors tightly coupled with the 7-series FPGA to enable faster communication interfaces development with ARM Design flow and hardware acceleration. Zynq devices are available in two categories viz. Zynq-7000s family FPGA for the cost-effective application such as IoT related applications while Zynq 7000 family FPGA are best for high-performance applications such as Embedded Vision etc. The Zynq 7000s comes with Single core ARM while Zynq 7000 comes with Dual-Core ARM.

This course covers fundamentals of Popular Xilinx drivers viz. UART, AXI Timers, UART16550, AXI GPIO, AXI BRAM, etc. The course also illustrates the usage of the AXI interrupt controller for handling Interrupts. Also to felicitate incorporation of Hardware accelerators with Zynq based design few examples on building Custom AXI Peripherals are also included. Software and Hardware Debugging, Profiling fundamentals are demonstrated with Zynq to felicitate performance measurement.

This course will create the foundation necessary to quickly start building applications on Zynq FPGA devices without prior experience in this domain. The entire course is a Lab-based course with a major focussed on building skills necessary to handle simple peripherals such as GPIO, Intermediate Peripherals such as UART PS, AXI BRAM, and complex Peripherals such as AXI Interrupt Controller, AXI Timers, GIC etc.

Who this course is for:

Anyone wish to build expertise in Xilinx Zynq APSOC and Xilinx VITIS Environment
Embedded System Design with FPGA Processors

Embedded System Design with Xilinx Zynq SoC and Vitis IDE

What you'll learn

Explore related topics

Course content

Installation7 lectures • 10min

Toolchain Configuration12 lectures • 1hr 8min

Simple Peripherals : Working with GPIO28 lectures • 2hr 19min

Working with UART13 lectures • 57min

Working with Timers / Counters33 lectures • 2hr 43min

Debugging Techniques13 lectures • 55min

Profiling9 lectures • 39min

Interrupts22 lectures • 2hr 7min

Requirements

Description

Who this course is for: