Embedded System Design with Xilinx Zynq FPGA and VIVADO
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- To Understand and Familiarize VIVADO Design Methodology and Zynq Architecture for FPGA Design.
- Rapidly architect an embedded system targeting the ARM processor of Zynq located on ZedBoard using Vivado and IP Integrator
- Create Custom AXI-4 Slave Led Controller IP with VIVADO IPI in VHDL.
- Software Design for Embedded Application with VIVADO and SDK
- To Create a bootable system capable of booting from the SD card and QSPI flash
- Debug designs with SDK and Utilize Timer Resources of Processing System.
- Design Custom Embedded System with Xilinx Zynq 7000 FPGA with VIVADO in VHDL
- Create Designs with VIVADO IPI and Implementing Design in ZedBoard FPGA.
- Design with VIVADO HLS and Export C/C++ Design into IP/RTL from HLS
- C Language Programming with Xilinx VIVADO SDK
- Hardware Description Language -HDL [VHDL/Verilog] basics
- Basic FPGA Design Flow
- Idea of Xilinx ISE Design Suit ( best if have idea of VIVADO design methodology)
- Basic Idea of Embedded Programming with C
- No Worries!!! we have introduced all the basics of VIVADO, Verilog/VHDL and Zynq in this Course!
Note: Course is updated with HLS Design Lab & Debugging Sessions.
Embedded System Design with Xilinx VIVADO Design Suit and Zynq FPGA is targeted for Hardware (FPGA) Design and Embedded enthusiast who want to upgrade and enhance their hardware(FPGA) Design Skills with State of Art Design Tools and FPGA from Xilinx. This course cover from Introduction to VIVADO, Intellectual Property (IP), IP Design Methodology, designing basic embedded system with Vivado and SDK, Creating custom AXI-4 Lite Led Controller IP, Programming Processing System (PS) of Zynq (i.e Zedboard) with Embedded Application projects from SDK , Utilizing Timer API and Debugging Features on SDK for Zynq PS, and Creating Boot Image of the Application Project for SD and QSPI flash of Zynq (ZedBoard).
Finally we have included the session on "Embedded Design with VIVADO HLS" this session includes the HLS Design Methodology, Synthesizing HLS C/C++ Project, Generating RTL/HDL from C/C++ and Exporting C/C++ project in to IP-XACT/ Pcore/Sys Gen Format.
So from this course you will able to get design/implementation skills of simple embedded system (Memory Test Application) to complex application design (utilizing Timer, Debugging etc.) and Create Bootable Image file of the application project.For more details please watch the demo video and some Free video of course.
- Electrical Engineering
- Computer Engineering and Computer Science
- Electronics Engineering
- Embedded System Design Enthusiast and Professionals
- Zynq Training Enthusiasts
VIVADO is sophisticated FPGA Design environment developed by Xilinx for its every (latest) FPGA Family. Previously there is ISE Design Suit which is little messy or complex and has less feature on design optimization and timing analysis. So VIVADO came out with latest state of art design methodology, functions and features all in one platform so the design engineer can excel and prototype fast for reducing overall design time (time to market will reduced by VIVADO).
VIVADO has included all the necessary options and menus on the left hand side. The main features of VIVADO is IP(Intellectual Property) Repository where lots of Xilinx IP and third IP can be customized and integrate with other logical block and components.
While Learning this course and performing with the LAB exercises, VIVADO has to be installed on PC. Vivado can be downloaded from Xilinx.com.For You OS type, You can install Webpack Version or System Edition of VIVADO including SDK and HLS, also include Zynq 7000 Board (select while installation). After installing VIVADO, you can get webpack version of license as (download 30 day evaluation license of vivado). After installation and License management you are ready for performing Lab on it.
This Course is Targeted for Zynq FPGA so you can use any of the Zynq FPGA Board's for Learning and performing lab session. In this Lecture session you will learn and add the Zybo Board Files on Your Vivado, so you can just click on Boards--> zybo instead of searching for xc7z010clg400-1 parts. So you can create a project and select the board just by one click.
We also have attached the "vivado-boards-master" with this session so you can use that zip file , extract it and follow the lecture for copying on the Xilinx/.../boards_files directory.
This Reference Guide on Verilog consists of detail explanation of Verilog Examples as Combinational Circuit and Sequential Circuit Design, ALU Design, Counter Design,State Machine Design and Signal Processing Example. Each example consists of Verilog Examples, Testbenchs and Example Output.
This Reference Guide Explains the VHDL Programming Methodology with Examples. Started with Basic Combinational Circuit (gates, decoder, multiplexer) to Sequential Circuit and Signal Processing Projects. This reference Guide also consists of Simulation testbench of all examples and schematic, block diagram.
In this first LAB session we are going to design a combinational circuit in VHDL (we have provided the Verilog sources in the attachment). We start with creating new project, adding new design source, synthesizing design , inserting constraint (constraint for Zedboard while you can insert constraint for other development boards to as, Zybo) and implementing design then finally generating design.
After completing this lab you will be able to create new project, include design and constraint sources, synthesize , implement and generate design.
We also have implemented our first lab on Hardware/FPGA. We have included constraint for Zedboard so we have targeted the bitstream to the zedboard. You can watch the implemented project and its functionality on FPGA with this video.
This Lab is the Basic HDL Design lab targeting Zybo FPGA. While the Overall Design Flow is same as previous Lab (in Lecture 7). So if you have Zybo you can go through this Lecture. We have presented complete flow of basic HDL design , implementation, generation and configuring Zybo FPGA in this Lecture.
Embedded System is those system which are designed to do specific task or perform specific job. Embedded system examples can be differentiate from small washing machine, microwave oven, ABS in automotive to specialized military systems (Weapon control system, Guided system, tracking system).
Zynq is System on Chip FPGA Family from Xilinx which lies under Zynq 7000 family, there are xc7z010, xc7z020, 030, and 040 Zynq series for prototyping. Zynq consist of Processing System (PS:- Two ARM Cortex A9) and Programmable Logic (PL:- Traditional Xilinx 7 Series FPGA Core). So the PL can be utilized for High Speed interface and PS for Instructing those PL and Processing data to/from PL. So the Designer can implement algorithms for embedded processing job.
Lab on Memory Test Applicaition targeted for Zybo FPGA. We already have complete the similar lab targeted for ZeddBoard. In this lab a VIVADO IPI project with Zynq PS has been exported to SDK and a Memory test application template is used to program PS of Zybo.
In this lab 2, we have session on how to interface Processing System and AXI GPIO (AXI GPIO IP can be configured as input as switch/button or output as LED). We have interface AXI GPIO (buttons and switch with Zynq PS). After interface completes the design has to validate, create HDL wrapper, synthesize design, implement design and generate it. After generation completes we need to write a software for PS for instructing AXI GPIO for that the generated project has to export to SDK. In SDK we are going to write a software application after application project completes we have to program FPGA (Programmable Logic) with bit file and launch Application project on Processing System (PS of Zynq). After implementing the application project we can setup USB UART with FPGA board (ZedBoard/Zybo) and get updates of the AXI GPIO Address on the UART Terminal of SDK.
In this section we will get idea of Custom IP Design methodology on VIVADO. Advance Extensible BUS (AXI) Interface Protocols , actually it is data transfer serial protocol used all over latest FPGA which was developed and patented by ARM holding, UK. This AXI has adopted from AMBA protocol features while it has different revisions as AXI2.0 , AXI 3.0, AXI 4.0 etc and there are different data transfer mode on AXI as AXI Memory Mapped (memory transfer with memory addresses) and AXI Streaming (Just data transfer no memory location).
One more thing we need to know about AXI is there might have Master or Slave of AXI Terminals. AXI data can also be transferred as AXI Full, AXI Lite.
In this lab 3, we are going to create a Custom LED Controller IP on VHDL, this IP will be AXI Slave. VIVADO has new feature of Creating Custom IP in HDL or RTL this IP can be imported on the IP integrator Menu and integrate with Zynq PS and other master component (some time microblaze, a 32 bit RISC processor). This led controller IP created and packaged with IP Package and edit menu of VIVADO. After interfacing completes the project has to be validated, autosetup address editors and create HDL wrapper. After HDL created we can Synthesize the project and implement for ZedBoard/Zybo FPGA or other family of FPGA.
Introduction to Software Development with VIVADO SDK and written in Embedded C Language has been explained on this session. You will get what is Software Application for Embedded System, how to write those application with VIAVDO SDK after Exporting Design from VIVADO IP Integrator (VIVADO Main Program).
We will get to know about the SDK Features and Functions so that we can create new project, launch application on PS of FPGA with USB JTAG Cable.
Here we have short demonstration on Implementing our Custom LED Controller IP on FPGA. The FPGA is ZedBoard which is Zynq Family, you can even shange the constraint in Section 3 Lab 1 for other board and can program other FPGA Development Boards to. The Possible other Boards are ZedBoard, Zybo ,Pynq , Zc706 Dev. Boards.
Timer is the Functional Unit on Zynq Processing System which can be called using API on VIVADO SDK, the timer API has to called on the Software Application written in VIVADO SDK. This timer API can provide some time delay for controlling any GPIO's. Aside of Timer there is Debugging features include on VIVADO SDK , this debugging feature can run the current application project on Hardware and check line by line operation.
Zynq Processing System(PS) has Timer functionality block inside of it, this timer can be initialized and called from SDK program written in C Programming. In this overview and LAB we are going to utilize that Timer API for creating some sort of delay on Led Blinking Process.
We are going to utilize SDK debugging feature for debugging C program written in SDK.
The Software Application with the Bitstream can be encapsulate in Boot.bin file so that file can be run by Processing system of Zynq FPGA. Any Software Application can be converted in to Bootable file so that it can run from SD Card attached with the board. The PS part fetch and execute the Boot.bin or bootable file (which includes bitstream and software application) and perform the defined operation.
In this Session we are going to Create our Custom Bootable File of the previous project (hello world project). This bootable file can be transferred on the SD card and attach with Zynq Device (Zedboard or Zybo) so the device will run the Bootable File and execute (for that you might need to change some Jumper setting for SD Bootup).
This Session is Overview of High Level Synthesis (A C/C++ Design Approach on FPGA Design), we have implemented Counter Design on C++ with VIVADO HLS (VIVADO HLS comes with VIVADO you just need to add it from add feature menu of VIVADO). The HLS Tool convert the C/C++ Design in to VHDL/Verilog and System C just after the click on Synthesize Design with HLS. We can generate IP Core or System Generator IP core from HLS which can be imported on VIVADO IP Integrator.
Tcl is Tool Command Language powerful Scripting Language (as BASH on Linux) for FPGA Design. VIVADO supports and allows to use Tcl command to do all the process GUI based operations. Correspodingly VIVADO also generates the Tcl commands of the GUI based operation. As example while we go through create new project option (GUI) , on the Tcl Console VIVADO also generates the corresponding Tcl command of that GUI based operation( Creating New Project).
Tcl provides FPGA Designer to optimize the design on resource and reduce design time cause it take less time to execute any process than GUI based operation.
This Section and Lecture will taught and make you familiar with Tcl, Basic Tcl command for creating project, processing , synthesizing etc. We also have Lab sessions for How to create Tcl command file from VIVADO Tcl console and How to run previously created or downloaded (created by another VIVADO) Tcl file to create projects. We also talk on Version Control of Tcl File according to VIVADO.
We also have attached the "Reference Guide on Tcl" Prepared by Digitronix Nepal with this Section.
In this Lab session you are going to create a Project of "Half Adder" with Tcl commands. We have provided the Tcl command and instruction in the Lab81 Sources Zip File attached with this Video, Please download the Zip file and Follow the Lecture/Lab.
In this Lab 82 we are going to use the previously created Tcl file (bcd_counter_tcl.tcl) for Creating , Adding HDL Source, Constraint, Synthesizing , Implementing, and Generating Bitstream automatically.
We also have attached Lab 82 Sources.zip file with this Lecture/Lab please download the Zip file and Follow the Lecture/Lab. We also have talk on Version Control of Tcl and VIVADO in this Session.
This Reference Guide explains about the Tcl commands, their examples and Output with Remark and Reference. We would like to request you to also visit UG835 from Xilinx and Wiki of Tcl and Tk. The Reference Guide has objective to introduce the Tcl Programming Language while this language can be used on the VIVADO Tcl Console for all types of operation there( Creating New project to generate and configure hardware).