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2021-02-08 14:52:48
30-Day Money-Back Guarantee
IT & Software Hardware Embedded Systems

Embedded System Design with Microblaze for Newbie

All about Xil Drivers, Interrupts, Custom AXI Peripherals , Debugging and Profiling
Hot & New
Rating: 5.0 out of 55.0 (2 ratings)
13 students
Created by Kumar K.
Last updated 2/2021
English
English [Auto]
30-Day Money-Back Guarantee

What you'll learn

  • Embedded System Design flow using Microblaze Soft Processor
  • Development of C applications for Microblaze Devices
  • Software and Hardware Debugging
  • Handling Interrupts in Microblaze based designs
  • Understanding Xilinx Drivers
  • Profiling

Requirements

  • Understanding of Digital Electronics
  • Fundamentals of Computer Architecture

Description

A faster Reconfigurable system makes FPGA a prominent choice for a large set of applications, but Hardware alone is incomplete without smart software synchronizing all the events fruitfully to achieve the desired Application. This course covers fundamentals of Popular Xilinx drivers viz. UART, AXI Timers, UART16550, AXI GPIO, AXI BRAM, etc. The course also illustrates the usage of the AXI interrupt controller for handling Interrupts. Also to felicitate incorporation of  Hardware accelerators with Microblaze based design few examples on building Custom AXI Peripherals are also included. Software and Hardware Debugging, Profiling fundamentals are demonstrated with Microblaze to felicitate performance measurement.

The Microblaze is an FPGA-based Soft Processor capable of executing single instruction per cycle with few exceptions. The MicroBlaze interconnect is reconfigurable capable of communicating with a large set of peripherals to fit most of the medium-scale applications. It allows configuration of cache size, pipeline depth, peripherals, memory management unit, and bus interface suitable to fit different application requirements. As systems complexities are growing day by day, Microblaze will play central role in the non-Zynq based FPGA families whereas it will be the best light-weight alternative working in tandem with the Zynq hard processor for Zynq and Ultrascale based FPGA families.

Who this course is for:

  • Anyone wish to build expertise in Xilinx Microblaze Devices and Vivado SDK Environment
  • Embedded System Design with FPGA Soft Processors

Course content

9 sections • 32 lectures • 5h 57m total length

  • GIT Reporsitory with Vivado 2017.4 Project files for the Course
    00:00

  • Preview18:17
  • Usage of TCL Script for Automation
    08:57
  • Understanding useful Files added to Project Directory
    03:50

  • Preview18:47
  • Reading Data from Peripherals
    07:51
  • How to use multiple instances of Peripheral IP
    09:39
  • How to use Dual Channel in Peripheral IP
    04:55

  • Working with UART16550 : Baud rate configuration and handling format structure
    17:43
  • Working with UART16550 : Operating Mode Configuration
    07:30
  • Code
    00:38
  • Working with AXI Timer
    15:35
  • SDK Code
    00:15

  • Profile with AXI Timer Part 1
    03:42
  • Debugging existing Settings
    04:08

  • Using AXI Block Memory
    18:43
  • Using external DDR
    08:01

  • Overview of ILA with ZYNQ
    21:35
  • Differences in ILA with Pure Verilog RTL
    06:38
  • Using ILA with Microblaze : Understanding Write Transaction
    18:07
  • Using ILA with Microblaze : Understanding Read Transaction
    01:02
  • Debugging with Serial Terminal
    02:39
  • Breakpoint and Memory Viewer usage
    14:24
  • Xilinx Software Command line Tool (XSCT) usage
    10:30

  • Preview09:33
  • Using GPIO Interrupt
    25:24
  • Code
    00:19
  • Using Watchdog Timer Interrupt
    25:34
  • Resetting Microblaze after WDT rollout
    02:55
  • Using AXI Timer Interrupt
    21:25

  • Using AXI Slave Lite Interface
    26:09
  • Adding I/O ports to AXI Slave lite Interface
    22:14

Instructor

Kumar K.
FPGA Developer Lead at FinTech
Kumar K.
  • 4.5 Instructor Rating
  • 164 Reviews
  • 1,022 Students
  • 8 Courses

I am working as FPGA Developer Lead in India's Finest Financial Technology Firm for the development of a next-generation High-Frequency Trading platform on Xilinx Alveo FPGA Cards. Before Joining Fintech, I spent three years as a VLSI Trainer at Mumbai University, India, and one year as Research Scientist at the Prominent R&D Centre for Applied Electronic Research of India contributing to the development of  Gradient Controller,64 Mhz Receiver on FPGA for Indigenous MRI Machine. During my free time, I love to develop Udemy Courses. I also collaborated with Larsen & Toubro Technology Services, Power International in the development of various FPGA based Systems such as Simultaneous DAQ, Multi-channel Logic Analyzers, and DTS. My area of interest includes Front End VLSI Design, SoC, and Chip Verification.

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