Embedded System Design with Microblaze and Vitis IDE

Explore the embedded system design field through a simple helloworld console example and a step-by-step process, including various project types and key decision scenarios.

Explore design flow steps for an embedded system using microblaze and vitis ide, from ip integrator setup and block automation to validation and bitstream generation.

Export hardware for the design by selecting export hardware and specifying the project location, then launch the Vitis IDE and set the workspace for related files.

Create a platform project from the hardware design, export it to nyt, then build an application project and run hello world on the FPGA via the debug flow.

Explore the fundamentals of project types for embedded system design with Microblaze and Vitis IDE, covering example project, planning project, synthesis project, and ideal project.

Explore the flow navigator in Vitis IDE to manage project settings, add IP, choose text-based or IP-integrated design, and run simulation, synthesis, and bitstream flow.

Explore how the project directory organizes hardware and software data for a Microblaze design in Vitis IDE, with a sources folder for IPs, THORChain wrappers, and Gen4 blocks.

Update an existing hardware design by exporting and applying a new build support package, and configure GPIO to drive an LCD over a 16-bit interface with automated IP connection.

Update the hardware platform by selecting the platform project, applying hardware specifications, and building the project, then check the support package for updates.

Use a TCL script to automate the full workflow in microblaze design with Vitis IDE, from creating a project to building a block design and configuring IPs.

Explore three reporting mechanisms for output in embedded design with MicroBlaze and Vitis IDE, including constant strings, fixed-point values, and floating-point data.

Learn to configure gpio instances using fixed and instance structures, write to and read from gpio via vip, manage multiple gpio ip blocks, and enable dual-channel gpio in c applications.

Explore how to initialize and use xil drivers across simple to complex cases, outlining a standard init format, data structures, gpi/gpo configuration, and api-based application building.

Initialize xil drivers by declaring an instance and a config structure, populate the config via lookup config using the device ID, then call cfd initialize and verify.

Declare and initialize the instance and config structures, look up the device config, and initialize the driver; verify status and report device initialization success using the xil drivers workflow.

Design a microblaze-based gpio p1 writer by configuring a 16-bit gpio ip, driving a one-second blink, and validating pin connections before synthesis.

Open synthesis design, review device and package, analyze key labels, and confirm ports are correctly mapped to pins for GPIO P2 data writing and stream generation.

Learn how to configure gpio driver in a microblaze project with Vitis IDE, initialize gpio, set 16-bit gpio as output, and blink leds by writing 1s and 0s with delays.

Modify the IP to read the status from a GPIO P1 switch, automate the connection to the IP, update the block design, and generate the bitstream.

Read 16 GPIO switch values from a MicroBlaze project, update hardware specs and builds, and print the switch states to a serial terminal every second.

Learn to configure a dual channel GPIO P1 with MicroBlaze in Vitis IDE. Set channel one for switch input and channel two for data output, with port connections and validation.

Initialize the dual-channel GPIO on the Microblaze with Vitis IDE, configuring channel 1 as input from switches and channel 2 as a 16-bit output to LEDs, updating every second.

Create and configure multiple instances of the same IP to connect to a switch, rename and customize each instance, map ports, and generate the bitstream.

Set up a platform with two gpio instances, initialize switch and lcd drivers, configure directions, and run an app that reads the switch and displays on the lcd.

Learn intermediate uart configuration and debugging, covering initialization, sending and receiving data, multiple uart instances, operating modes, and on-the-fly updates for 16550 uart to build a foundation for advanced designs.

Configure uart p1 data transmission using advanced peripheral APIs, set parameters and operation mode, validate the design, map pins, and generate an hdl wrapper.

Learn to export hardware in Vitis, then implement a UART lite data transfer with a poll-based API that sends 16-byte chunks after initialization and self-test.

Receive data from UART by initializing an 11-byte buffer, using the receive API to fill it byte by byte, and then send the data back to the console.

Learn to use multiple UARTLITE instances in a Microblaze design, initialize two IP cores, connect across, send data from one IP to another, and validate the interface protocol for debugging.

Learn how to initialize and manage multiple uartlite IP instances, configure with lookup config structures, and verify bidirectional nine-byte data transfers between two uartlite peripherals.

Explores configuring and integrating the UART16550 IP in a MicroBlaze design using Vitis IDE, including baud settings, port connections, block design validation, and generating the bitstream via a new workspace.

Configure and test the uart16550 p2 driver within a microblaze and vitis ide workflow. Set baud rate, enable loopback mode, and verify transmitted data.

Learn to configure complex variants and compare them with intermediate variants. Explore timer options, including a timer and a one stop time, and set up the mode to start working.

Configure the AXI timer P1 in the MicroBlaze design, enable a single timer, interface it with MicroBlaze using Vitis IDE, and validate the design before generating the source.

Configure the AXI timer in Vitis by looking up the device, initializing with a self-test, setting a count down delay, then start and poll expiry.

Observe the timer counter in a MicroBlaze Vitis IDE project by querying the current value via an API, printing at intervals, and validating a downward count through hardware execution.

Utilize auto reload mode to generate events every five seconds by reloading the counter when it hits zero and restarting the timer, producing recurring console output.

Explains using multiple timers with microblaze in Vitis IDE, including initialization, configuration, and running two timers with two and five second delays, plus stop, reset, and self-test steps.

Learn to implement PWM with a 50% duty cycle using MicroBlaze and Vitis IDE, configuring 32-bit counters, timers, and block designs to generate stable outputs for lcds and speakers.

Open the synthesis site to analyze pools and attach pwm with 50% duty cycle to a fixed FPGA pin. Update constraints to map clock, reset, and USB signals.

Learn to set up a pwm with a 50% duty cycle using a timer, including initialization, configuration of the period and duty cycle, and proper enabling before operation.

Vary the duty cycle to create a fading LCD brightness by ramping from low to high intensity and back, using PWM configuration and timer-driven cycles.

Learn to generate a fading effect using a triangular waveform that ramps from low to high and back, controlled by count up/down with a period and a 30 ms delay.

Configure the AXI timebase watchdog timer p1 with the wtt parameter (8–31), compute delay from clock period, and generate wrapper, 11 seconds at wtt 30 with a 10 ns clock.

learn how to initialize and validate an AXI timebase watchdog timer using the WTT driver, including the lookup config function, CFD initialize, self-test, and handling WD expired events.

Learn to generate multiple watchdog timer events by periodically restarting the WDT with its restart function, while observing WD expiry during FPGA project execution.

Profile your embedded application to analyze the time each function consumes, and quantify either a specific function or all functions using the built-in profiling capabilities.

Configure the MicroBlaze design with an AXI timer to enable precise profiling by selecting a single timer, disabling the default second timer, and automating timer IP connections.

This lecture explains profiling a microblaze-based application with an AXI timer in Vitis IDE, covering initialization, configuration, start/stop, counting clock cycles, and converting to nanoseconds and microseconds at 100 MHz.

Discover how to run profiling with the sdk profiler for microblaze projects by configuring a profile timer and local memory, wiring timer to control, and validating across applications.

Enable SDK profiling for the MicroBlaze project by adjusting BSP settings, enabling the profile timer, adding flags, disabling garbage collection, and running a single-application debug to capture function-level profiling data.

Explore byte addressable memory versus word addressable memory, where each memory location or word has a unique address and word size varies with cpu architecture.

Learn to add BRAM IP to a block design to enable fast read and write, connect the RAM controller, configure depth and width, and generate a hello world template.

Learn to perform BRAM transactions in a Microblaze design using pointers: initialize the memory driver, write and read 50 samples, and verify data in Vitis IDE.

Demonstrates bram transactions using XIL_IO drivers by reading and writing 16-, 32-, and 64-bit values via addresses, comparing pointer and XIL_IO methods, and validating data.

Explore hardware debugging with an integrated logic analyzer to observe transactions and signal transitions on nets inside a microblaze design in Vitis IDE.

Use the integrated logic analyzer to export the bitstream and build a GPIO platform project in Vitis IDE, then debug hardware by observing and analyzing transactions.

Adjust the integrated logic analyzer’s sample depth from the default 1024 to 2048, mindful of bram slices and ram usage, via the hardware manager.

Use a serial terminal to observe inputs, outputs, and variables in a Microblaze project with Vitis IDE, and learn print formats for integers and floating point debugging.

Explore the agenda by examining the driver fundamentals, configuring different functions, and demonstrating how GPIO will interpret high-priority events in embedded design.

Enable and connect an interrupt controller IP (INTC) to the MicroBlaze using Vitis IDE, configure GPIO P1 as the interrupt source, and monitor the interrupt state via the console.

Explore initializing the GPIO and internal controller, enabling exception handling, and handling an interrupt to read a switch and print its value to the console.

Configure an AXI timer interrupt in a MicroBlaze design using Vitis IDE, connect the interrupt controller, validate the design, generate the bitstream, and create a new application project.

Initialize the AXI timer and INTC, enable the exception handler, and set up a callback-driven interrupt; discuss handling when a global enable is unavailable and compare with watchdog timer.

Explore how to configure a watchdog timer in a MicroBlaze design using Vitis IDE, including setting the 32-bit counter, triggering interrupts, and reset behavior on expiry.

Initialize the watchdog timer driver and IPC, set up exception handling and interrupt callbacks, acknowledge and disable further interrupts after a single WDT event, and restart to generate multiple interrupts.

Explore how a watchdog timer prevents deadlock by resetting the system when timeouts occur, returning the application to the initial state on an fpga using Vitis IDE.

Learn to design embedded systems with custom ip cores, implement handshaking across slimline and slingblade interfaces, and explore lighting, full, and stream interfaces for designs with microblaze and vitis ide.

Create a slave AXI lite interface for a Microblaze design in Vitis IDE by packaging a template IP, configuring 32-bit registers, and implementing read/write logic for master transactions.

Create a slave AXI lite interface with microblaze in Vitis IDE by exporting hardware, modifying the makefile, and building a custom IP driven application.

Learn how to add a slave AXI LITE port to a custom IP by creating and packaging the IP, declaring a 16-bit data register, and mapping inputs and outputs.

Explore synthesis steps, open synthesis, and add pins for AXI lite slave interface and LCD peripherals. Map pins to FPGA package and generate a constrained bitstream with an XDC file.

Extend a microblaze design by adding a port to a slave AXI lite interface, map it to the IP base address, and perform register writes to drive a blinking output.

Create a slave axi stream interface for 32-bit data using a two-state FSM with tvalid, tready, tdata, tlast, and tstrb; package and validate the streaming ip.

Create an AXI stream interface by building the hardware platform, initializing the microblaze, and performing a polling transmit to verify data transfer.