Embedded Systems Bootcamp: RTOS, IoT, AI, Vision and FPGA

Explore combinational logic and basic gates, including and, or, and not, through truth tables and input-output behavior, contrasting with sequential logic in digital design.

Design combinational logic circuits using and, or, and not gates with switches, a power source, and a load, and analyze gate dependencies to predict circuit behavior.

Explore complex gates such as xor, nand, and nor, learn how their truth tables determine outputs for different signal inputs, and understand their role in designing electronic circuits.

Download the Quarkus web edition, install Quartus Prime for Cyclone V, create an Intel account, and place the files together prior to setup to enable the devices option.

Design a 4-bit equality checker used in logic design and cpus, using four xnor gates to compare bits and a final and gate to output one when all bits match.

Learn the basics of VHDL by implementing a two-input and gate, configuring a project, and simulating with ModelSim Altera to verify all input combinations.

Change the keyword to or to design a two-input or gate in VHDL, save the file as or gate, and set it as the top level entity for compilation.

Build a three-input xor gate by cascading xor operations, create a top entity, compile, and generate a test bench with eight input combinations, then simulate to verify behavior.

Learn how multiplexers route data from multiple inputs to a single output using a select line, and how demultiplexers invert this routing, with a four-input, multi-bit example.

Design a 2-to-1 multiplexer from basic gates by building a schematic with and, or, and not gates, wiring inputs i0, i1 and the select line, and verify with waveform simulation.

Explains building and simulating a 2-to-1 eight-bit multiplexer in VHDL, including the entity, architecture, and a behavioral design with std_logic_vector inputs and data out.

Master binary representation by converting bits to numbers, exploring unsigned ranges for two- and three-bit systems, counting in binary, and introducing second complements for negatives.

Explore signed binary addition and subtraction using the second complement form, convert subtraction to addition, and understand overflow when results exceed the bit width.

Explore half adders and full adders, and see how two half adders create a full adder with a carry input. Learn to derive sum and carry from truth tables and implement with xor, and, or, and not gates.

Build a half adder from an xor gate and an and gate, with inputs A and B producing sum and carry, then test all four input combinations.

Instantiate a black box from a half adder to implement a one-bit full adder, then simulate its sum and carry out with inputs A, B, and carry in.

Grounding inputs in a four-bit adder simulation shows why carry-in must be zero to avoid uncertain results. Grounding the first carry-in fixes the output, yielding 0111 for 3 plus 4.

Learn to combine multiple signals into a single bus by grouping and reversing bit order to form 3..0 vectors (a, b, sum) for simulation and real circuit implementation.

Extend a 1-bit adder by cascading half adders into full adders to create a four-bit adder, wiring carries and sums through an alu-like block used in cpu and gpu architectures.

Examine how adding signed numbers works by representing negatives in binary, treating subtraction as addition, and noting how unsigned versus signed views and four-bit versus longer bit-length alter results.

Explore VHDL design styles—structural, data flow, and behavioral—and learn how each maps hardware from gates to prototyping, using high-level behavior for rapid FPGA modeling.

Casting in VHDL converts data types, such as std_logic_vector to unsigned or integer, via a defined sequence; signed and unsigned wrap at limits, while integers overflow and lack bit access.

Explore how an alu handles logical and arithmetic operations with two inputs and an operation mode, producing a final result, and learn masking techniques and vhdl testing.

Design an 8-bit behavioral alu in vhdl using unsigned and signed types, with numeric_std, controlled by a case statement for add and subtract, and verify wrap-around via simulation.

Learn to detect ALU overflow by extending eight-bit operands to nine bits, cover unsigned and signed cases, and use a temp signal with carry out while debugging chunk by chunk.

Implement xor and xnor operations in the ALU and compare A and B to drive conditional results, using 8-bit outputs and behavioral and structural design approaches.

Master the VHDL process keyword to execute code sequentially within a sensitivity list for state machines and behavioral design.

Compare combinational logic with sequential logic, noting no memory or feedback in combinational designs. Explain how sequential logic uses feedback to memory elements and clocks to store states.

Explore the sr latch as a memory element; learn how set and reset inputs with nor or nand gates store and retain q and q̄ outputs.

Explore how an SR latch using NOR gates maintains state, tracing initial, set, and reset conditions from a node truth table, and explain why the not allowed state cannot occur.

Demonstrate a data flow SR latch design in VHDL, defining S, R, and Q and internal Q hat, addressing inout feedback and a basic simulation.

Learn to build a d latch with a behavioral VHDL approach, showing how clock enable controls q to follow d and how the latch retains its value between clock cycles.

The D flip flop builds on a latch with enable-controlled and gates to manage set and reset, preventing not-allowed states and showing level-detection gating toward clocked storage.

Explore clock timing in synchronous designs, compare level based and edge based triggering, and explain rising and falling edges that drive flip flop behavior and finite state machines.

Explore finite state machines as sequence controllers for digital circuits, using ALU, registers, and a multiplexer to automate operations and implement sequence detectors.

presents a project that blends structural and behavioral design, using an alu and an fsm to perform operations on registers a, b, and c, with a reset.

Design a block diagram to interconnect ALU, multiplexer, flip-flops, and an FSM from a library of components, then compile and simulate the data flow.

Interconnect all components per the diagram by wiring the ALU, registers (A, B, C), and the multiplexer via a bus, then simulate by manually adding inputs and monitoring outputs.

demonstrate data flow and feedback in an embedded alu design by adding A and B, then adding rc with B using a select line and latching results.

Design a finite state machine in vhdl by defining a state type, current and next state pointers, and two parallel processes for clocked transitions and state updates.

Explore a two-process state machine running in parallel, using reset and states such as init, fetch, process, write result, and accumulate to drive clocked transitions and simulate this block early.

Test and debug a finite state machine by compiling, fixing syntax errors, and simulating transitions; encode five states in a three bit state out signal for clear visualization.

Develop and simulate an 8-bit alu via a finite state machine, integrate signals, create a block diagram, and verify clock-driven write, accumulate, and operation steps.